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Patent # Description
US-9,741,614 Method of preventing trench distortion
A method of forming trenches and a via by self-aligned double patterning includes providing a dielectric layer covered by an SiOC layer, a TiN layer and a SiON...
US-9,741,613 Method for producing self-aligned line end vias and related device
A method for producing self-aligned line end vias and the resulting device are provided. Embodiments include forming trenches in a dielectric layer; filling the...
US-9,741,612 Semiconductor devices and methods for backside photo alignment
Various embodiments of microelectronic devices and methods of manufacturing are described herein. In one embodiment, a method for aligning an electronic feature...
US-9,741,611 Method of forming semiconductor device including protrusion type isolation layer
A semiconductor device may include a semiconductor layer having a convex portion and a concave portion surrounding the convex portion. The semiconductor device...
US-9,741,610 Sacrificial amorphous silicon hard mask for BEOL
A starting metallization structure for electrically coupling one or more underlying semiconductor devices, the structure including a bottom layer of dielectric...
US-9,741,609 Middle of line cobalt interconnection
A method of fabricating features of a semiconductor device includes forming a contact over a substrate, the contact including a cobalt core and a liner layer...
US-9,741,608 Methods of fabricating semiconductor devices including supporting patterns in gap regions between conductive...
An integrated circuit device includes spaced apart conductive patterns on a substrate surface, and a supporting pattern on the substrate surface between...
US-9,741,607 Photo pattern method to increase via etching rate
Semiconductor devices are provided having large vias, such as under bonding pads, to increase the via open area ratio, increase the via etching rate, and avoid...
US-9,741,606 Desmear with metalized protective film
Embodiments herein may relate to a technique for generating a via in a substrate. Specifically, the technique may include coupling a polyethylene terephthalate...
US-9,741,605 Reducing defects and improving reliability of BEOL metal fill
A method of reducing defects in and improving reliability of Back-End-Of-Line (BEOL) metal fill includes providing a starting metallization structure for...
US-9,741,604 MOSFETs with channels on nothing and methods for forming the same
A method includes performing an epitaxy to grow a semiconductor layer, which includes a top portion over a semiconductor region. The semiconductor region is...
US-9,741,603 Method for producing hybrid substrate, and hybrid substrate
A hybrid substrate has an SOI structure having a good silicon active layer, without defects such as partial separation of the silicon active layer is obtained...
US-9,741,602 Contact for a non-volatile memory and method therefor
A semiconductor device is disclosed that comprises a first non-volatile memory cell, a second non-volatile memory cell, an active region between the first and...
US-9,741,601 Semiconductor component with regions electrically insulated from one another and method for making a...
Semiconductor component comprising at least two semiconductor regions are disclosed. In one embodiment the semiconductor regions of the semiconductor component...
US-9,741,600 Semiconductor apparatus with transportable edge ring for substrate transport
An apparatus and method for processing semiconductor substrates provides a substrate stage being a rotatable disc with a solid surface and a terraced edge with...
US-9,741,599 High voltage chuck for a probe station
A chuck for testing an integrated circuit includes an upper conductive layer having a lower surface and an upper surface suitable to support a device under...
US-9,741,598 Protective tape and method for manufacturing a semiconductor device using the same
A protective tape and a method for manufacturing a semiconductor device using the same capable of achieving excellent connection properties. The protective tape...
US-9,741,597 Positioning device for glass substrate
The present invention provides a positioning device configured to position a glass substrate. The positioning device comprises a support base, a pair of first...
US-9,741,596 Bonding apparatus and bonding process method
According to one embodiment, a bonding apparatus for processing a retained substrate includes a main body unit, a nozzle, a gas supply unit, and a substrate...
US-9,741,595 Bonding method, storage medium, bonding apparatus and bonding system
There is provided a method of bonding substrates to each other, which includes: holding a first substrate on a lower surface of a first holding part; adjusting...
US-9,741,594 Substrate processing apparatus and substrate processing method for performing heat treatment on substrate
Each of substrates which are sequentially loaded into an apparatus is transferred to one of empty (available) cooling units, and the cooling unit is reserved as...
US-9,741,593 Thermal management systems and methods for wafer processing systems
A workpiece holder includes a puck having a cylindrical axis, a radius about the cylindrical axis, and a thickness. At least a top surface of the puck is...
US-9,741,592 Micro device stabilization post
A method and structure for stabilizing an array of micro devices is disclosed. The array of micro devices is formed on an array of stabilization posts formed...
US-9,741,591 Wafer level packaging of microbolometer vacuum package assemblies
An apparatus for the wafer level packaging (WLP) of micro-bolometer vacuum package assemblies (VPAs), in one embodiment, includes a wafer alignment and bonding...
US-9,741,590 Stack frame for electrical connections and the method to fabricate thereof
A method for forming a conductive structure is disclosed, the method comprising the steps of: forming a metallic frame having a plurality of metal parts...
US-9,741,589 Substrate pad structure
A structure comprises a plurality of top pads protruding over a top surface of a package substrate, wherein a top pad comprises a first half-circle portion, a...
US-9,741,588 Method of manufacturing thin-film transistor substrate
A method of manufacturing a thin-film transistor substrate which includes a thin-film transistor includes: forming a planarization layer comprising polyimide...
US-9,741,587 Semiconductor device and semiconductor device manufacturing method
Provided are a semiconductor device manufacturing method and semiconductor device such that manufacturing can be simplified and the thickness of the...
US-9,741,586 Method of fabricating package structures
Some embodiments contemplate methods for forming a package structure and a package structure formed thereby. An embodiment method includes depositing a...
US-9,741,585 Reactive radical treatment for polymer removal and workpiece cleaning
A method for removing polymer is provided. An aqueous solution is applied to a semiconductor workpiece with polymer arranged thereon. The aqueous solution...
US-9,741,584 Densification of dielectric film using inductively coupled high density plasma
A method for densifying a dielectric film on a substrate includes arranging a substrate including a dielectric film on a substrate support in a substrate...
US-9,741,583 Substrate treatment method, computer readable storage medium and substrate treatment system
A substrate treatment method includes: forming a plurality of circular patterns of a resist film on a substrate; thereafter applying a first block copolymer;...
US-9,741,582 Method of forming a semiconductor device including a pitch multiplication
Disclosed herein is a manufacturing method of a semiconductor device that includes forming first and second layers over an underlying martial such that the...
US-9,741,581 Using tensile mask to minimize buckling in substrate
A method for preventing buckling in a substrate using a tensile hard mask is provided. The method may include forming a mask over a substrate, the hard mask...
US-9,741,580 Substrate mask patterns, methods of forming a structure on a substrate, methods of forming a square lattice...
A method of forming a pattern on a substrate comprises forming spaced, upwardly-open, cylinder-like structures projecting longitudinally outward of a base....
US-9,741,579 Plasma processing apparatus and plasma processing method
A plasma processing apparatus includes a sample stage disposed in a processing chamber within a vacuum chamber. A wafer mounted on a top surface of the sample...
US-9,741,578 Manufacturing method of semiconductor device
A technique of reducing the contact resistance between a semiconductor substrate and a metal layer is provided. A manufacturing method of a semiconductor device...
US-9,741,577 Metal reflow for middle of line contacts
A method of forming a contact in a semiconductor device includes forming a first gate and a second gate on a substrate; removing an interlayer dielectric (ILD)...
US-9,741,576 Light irradiation type heat treatment method and heat treatment apparatus
A metal film is deposited on a front surface of a semiconductor wafer of silicon. After the semiconductor wafer is received in a chamber, the pressure in the...
US-9,741,575 CVD apparatus with gas delivery ring
The present disclosure relates to a chemical vapor deposition apparatus and associated methods. In some embodiments, the CVD apparatus has a vacuum chamber and...
US-9,741,574 Cyclic deposition method for thin film and manufacturing method for semiconductor, and semiconductor device
Provided is a method of cyclically depositing a thin film including: performing an oxide depositing operation of repeatedly performing a deposition operation, a...
US-9,741,573 NAND flash memory and fabrication method thereof
A method is provided for fabricating a NAND flash memory. The method includes providing a semiconductor substrate having an isolation material layer formed on...
US-9,741,572 Method of forming oxide layer
A method of forming an oxide layer is provided in the present invention. The method includes the following steps. A first oxide layer is formed on a...
US-9,741,571 Bipolar transistor device with an emitter having two types of emitter regions
Disclosed is a bipolar semiconductor device, comprising a semiconductor body having a first surface; and a base region of a first doping type and a first...
US-9,741,570 Method of manufacturing a reverse-blocking IGBT
A method of manufacturing a reverse-blocking IGBT (insulated gate bipolar transistor) includes forming a plurality of IGBT cells in a device region of a...
US-9,741,569 Forming memory using doped oxide
A method is provided for manufacturing a memory device. A strip of semiconductor material is formed having a memory region, a contact landing area region and a...
US-9,741,568 Sulfur doping method for graphene
The invention provides a sulfur doping method for graphene, which comprises the steps of: 1) providing graphene and placing the grapheme in a chemical vapor...
US-9,741,567 Method of forming multiple patterning spacer structures
Disclosed herein is a method of forming a structure, comprising forming a mandrel layer over a substrate, masking the mandrel layer with a first mask and...
US-9,741,566 Methods for manufacturing a spacer with desired profile in an advanced patterning process
Embodiments herein provide apparatus and methods for performing an etching process on a spacer layer with good profile control in multiple patterning processes....
US-9,741,564 Method of forming mark pattern, recording medium and method of generating mark data
In a method of forming a mark pattern according to the embodiments, a film to be processed on a substrate is coated with a photosensitive film, and the...
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