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Patent # Description
US-9,741,461 Contact pins for glass seals and methods for their production
Contact pins for glass seals is provided having an iron alloy and a method for their production. The contact pins are provided with a nickel layer and coated...
US-9,741,460 Abyssal sequestration of nuclear waste and other types of hazardous waste
A system and method of disposing nuclear waste and other hazardous waste includes means for, and the steps of, blending a waste stream, which includes either a...
US-9,741,459 Modularized process flow facility plan for storing hazardous waste material
A modularized system for processing, storing and/or disposing of a hazardous waste material is described. In one exemplary embodiment, the modularized system...
US-9,741,458 Multimodal debris trap
In a debris trap that may be used in an Emergency Core Cooling System of a nuclear power plant, the filter media is arranged to define both filtration and...
US-9,741,457 Method and apparatus for the generation, heating and/or compression of plasmoids and/or recovery of energy...
Method and apparatus for heating and/or compressing plasmas to thermonuclear temperatures and densities are provided. In one aspect, at least one of at least...
US-9,741,456 Electronic device
An electronic device including a semiconductor memory unit that includes: a first access line coupled to a first memory cell; a second access line coupled to a...
US-9,741,455 Semiconductor memory device and operating method thereof
A semiconductor memory device includes: a cell array region storing and outputting data selected based on an input address and including a first cell region...
US-9,741,454 Semiconductor memory device and method of operating the same
A semiconductor memory device includes a memory cell array having a first group of main blocks, a second group of main blocks and redundancy blocks replacing...
US-9,741,453 Prober chuck for magnetic memory, and prober for magnetic memory provided with said chuck
There is provided a prober chuck capable of carrying out low leakage evaluation on a magnetic memory under environment in which a magnetic field is applied. A...
US-9,741,452 Read-assist circuits for memory bit cells employing a P-type field-effect transistor (PFET) read port(s), and...
Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are...
US-9,741,451 Data storage device and data maintenance method thereof
A data storage device including a flash memory and a controller. The flash memory includes a plurality of chips, each of the chips includes a plurality of...
US-9,741,450 Memory comprising a circuit for detecting a glitch on a line of the memory
A memory including at least one line to which memory cells are coupled. A control circuit is configured to emit an end-of-operation signal at the end of the...
US-9,741,449 Sample and hold circuit
Aspects of various embodiments of the present disclosure are directed to applications utilizing voltage sampling. In certain embodiments, a sample and hold...
US-9,741,448 Three-dimensional offset-printed memory with multiple bits-per-cell
The present invention discloses a three-dimensional offset-printed memory (3D-oP) with multiple bits-per-cell. The mask-patterns for different bits-in-a-cell...
US-9,741,447 Semiconductor device including fuse circuit
Disclosed here is a semiconductor device that comprises a plurality of input nodes configured to be supplied with input signals, a decoder coupled to the input...
US-9,741,446 Memory system with small size antifuse circuit capable of voltage boost
A memory system includes a control block, an antifuse voltage generator, an array voltage generator, and a memory array. The control block is used to output...
US-9,741,445 Cut layer programmable memory
Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a bitline. The integrated circuit may include...
US-9,741,444 Proxy wordline stress for read disturb detection
Methods and systems are provided where non-volatile solid state memory may include selected memory cells coupled to a selected word line and proxy memory cells...
US-9,741,443 Memory controller and system including the same
A memory controller according to an example embodiment of the present disclosure may include a duty ratio adjusting circuit which generates adjusted clock...
US-9,741,442 System and method of reading data from memory concurrently with sending write data to the memory
A data storage device includes a memory, a controller, and a communication bus coupled to the memory and to the controller. The controller is configured to send...
US-9,741,441 Nonvolatile memory system including nonvolatile memory device and memory controller and operating method of...
A nonvolatile memory system includes a nonvolatile memory device including a plurality of memory cells, and a memory controller. The memory controller is...
US-9,741,440 Memory device and read method of memory device
In a method of reading a memory device, difference information is generated based on a distance difference between a position of a read word-line and a position...
US-9,741,439 Non-volatile semiconductor memory device
According to one embodiment, a non-volatile semiconductor memory device comprises a memory cell array and a memory region. The memory cell array has a plurality...
US-9,741,438 Nonvolatile memory device and program method thereof
A nonvolatile memory device includes at least two strings that are vertically stacked on a substrate and share one bit line. A program method of the nonvolatile...
US-9,741,437 Semiconductor memory device and operating method thereof
Disclosed are a semiconductor memory device, and an operating method thereof. The semiconductor memory device includes: a memory cell array including a...
US-9,741,436 Dynamically controlling an operation execution time for a storage device
In general, this disclosure is directed to techniques for adjusting the timing of operations for a storage device. According to one aspect of the disclosure, a...
US-9,741,435 Sense amplifier circuit
A sense amplifier circuit includes a sampling capacitor coupled to the input of an inverting amplifier. The output of the inverting amplifier is coupled to a...
US-9,741,434 Resistance change memory
According to one embodiment, a memory includes a memory cell array including blocks arranged in a column direction, first and second main global conductive...
US-9,741,433 Apparatuses and methods for bi-directional access of cross-point arrays
The disclosed technology generally relates to apparatuses and methods of operating the same, and more particularly to cross point memory arrays and methods of...
US-9,741,432 Accessing memory cells in parallel in a cross-point array
Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first...
US-9,741,431 Optimal read threshold estimation
An optimal read threshold estimation method includes determining a flip difference corresponding to an optimal step size .DELTA..sub.opt, estimating a first...
US-9,741,430 Static random access memory with reduced write power
A static random access memory (SRAM) features reduced write cycle power consumption. The SRAM includes an array of static storage cells and a write controller....
US-9,741,429 Memory with write assist circuit
A memory device with an array of memory cells, a write driver circuit, and a write assist circuit is disclosed. The write driver circuit and the write assist...
US-9,741,428 Integrated circuit devices and methods
An integrated circuit can include multiple SRAM cells, each including at least two pull-up transistors, at least two pull-down transistors, and at least two...
US-9,741,427 Performing logical operations using sensing circuitry
Apparatuses and methods for performing logical operations using sensing circuitry are disclosed. An apparatus comprises an array of memory cells, sensing...
US-9,741,426 Semiconductor memory device
A semiconductor memory device may include: a plurality of memory mats; and a plurality of sense amplifier arrays arranged alternately with the memory mats, each...
US-9,741,425 Memory device and memory system including the memory device
A memory device includes a first memory bank comprising first and second memory blocks; a second memory bank comprising third and fourth memory blocks; and a...
US-9,741,424 Memory controller
A memory controller component includes transmit circuitry and adjusting circuitry. The transmit circuitry transmits a clock signal and write data to a DRAM, the...
US-9,741,423 Methods and apparatus for synchronizing communication with a memory controller
A memory controller receives data and phase-providing signals from a memory device. The phase-providing signal is not a clock signal, but is used by the memory...
US-9,741,422 Device for controlling a refresh operation to a plurality of banks in a semiconductor device
A refresh control device may include a plurality of latch circuits configured to receive an active signal, a refresh signal, an active control signal, and a...
US-9,741,421 Refresh circuitry
The present disclosure includes apparatuses and methods related to refresh circuitry. An example apparatus can include a memory array including a main portion...
US-9,741,420 Skyrmion driving method and driving apparatus
A skyrmion driving method that utilizes electric current to make it possible to perform driving ON-OFF control at high speed and to suppress the influence of an...
US-9,741,419 Memory system with a content addressable superconducting memory
A memory system including a content addressable memory having an array of content addressable memory elements including a plurality of rows of content...
US-9,741,418 Write apparatus and magnetic memory
A write apparatus and a magnetic memory, where the write apparatus includes a first drive port, a second drive port, a first information storage area, a second...
US-9,741,417 Sense amplifier circuit
In one embodiment, a sense amplifier circuit includes two current paths. Each path includes a transistor configured as a current source during a memory read...
US-9,741,416 Memory devices based on gate controlled ferromagnestism and spin-polarized current injection
Memory devices based on gate controlled ferromagnetism and spin-polarized current injection are provided. The device structure can include a two dimensional...
US-9,741,415 Magnetic devices having insulating spacer that surrounds portion of wiring structure and variable resistance...
Disclosed are a magnetic device and a method of manufacturing the same. The magnetic device includes an insulation spacer that surrounds a portion of a wiring...
US-9,741,414 Spin orbit and spin transfer torque-based spintronics devices
A spin orbit torque-based spintronics device that includes a ferromagnet layer having a first surface and a second surface opposed to each other, a metal layer...
US-9,741,413 Methods of reading six-transistor cross-coupled thyristor-based SRAM memory cells
A six-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with methods of operation. Methods of increasing the...
US-9,741,412 Semiconductor apparatus
A semiconductor apparatus may include: a data storage group including first to eight data storage areas; a first channel select pad configured to transmit a...
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