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Patent # Description
US-9,740,645 Reducing latency in a peripheral component interconnect express link
A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the...
US-9,740,644 Avoiding premature enabling of nonmaskable interrupts when returning from exceptions
A processor of an aspect includes a decode unit to decode an exception handler return instruction. The processor also includes an exception handler return...
US-9,740,643 Systems and methods for recovering higher speed communication between devices
A method of operating a device is disclosed. The method includes attempting communication between the device and a separate connecting device. The attempt...
US-9,740,642 Methods and electronic devices for adjusting the operating frequency of a memory
Methods and electronic devices for adjusting an operating frequency of a memory are disclosed. The method includes: transmitting to the memory a first command...
US-9,740,641 Information processing device, I/O system, and I/O control method
An information processing device that are capable of continuing access to an I/O device by operational computers even when a failure has occurred in a...
US-9,740,640 System integrated teaming
A network teaming system includes one or more subsystems to provide a hardware system integrated teaming assistant (SITA hardware), provide a software system...
US-9,740,639 Map-based rapid data encryption policy compliance
To comply with a policy for a computing device indicating that data written by the computing device to the storage volume after activation of the policy be...
US-9,740,638 Systems and methods for preventing data remanence in memory
A system for preventing data remanence in memory is provided. The system includes a computing device, a memory chip coupled to the computing device and...
US-9,740,637 Cryptographic multi-shadowing with integrity verification
A virtual-machine-based system that may protect the privacy and integrity of application data, even in the event of a total operating system compromise. An...
US-9,740,636 Information processing apparatus
According to an embodiment, an information processing apparatus includes a plurality of cores, a shared resource that can be shared by the plurality of cores,...
US-9,740,635 Computing method and apparatus associated with context-aware management of a file cache
Computer-readable storage media, computing devices and methods associated with file cache management are discussed herein. In embodiments, a computing device...
US-9,740,634 Establishing a point-in-time copy relationship between source logical addresses and target logical addresses
Provided are a computer program product, system, and method for establishing a point-in-time copy relationship between source logical addresses and target...
US-9,740,633 Updatable address lookup application program interface
Embodiments relate to a new application program interface (API) and supporting tools to introduce efficiency associated with a transaction. An in-memory...
US-9,740,632 Snapshot efficiency
In one aspect, a method includes receiving a request to write to an offset in a first logical device, determining a second logical device that wrote to the...
US-9,740,631 Hardware-assisted memory compression management using page filter and system MMU
Provided are methods and systems for managing memory using a hardware-based page filter designed to distinguish between active and inactive pages ("hot" and...
US-9,740,630 Method of mapping address in storage device, method of reading data from storage devices and method of writing...
In a method of mapping an address in a storage device, first address mapping information including a first physical address and a first logical address is...
US-9,740,629 Tracking memory accesses when invalidating effective address to real address translations
According to embodiments of the present disclosure, a method for invalidating an address translation entry in an effective address to real address translation...
US-9,740,628 Page table entry consolidation
A method includes identifying, by a processor, a first page table entry (PTE) of a page table for translating virtual addresses to main storage addresses, the...
US-9,740,627 Placement engine for a block device
A system, method, and computer program product are provided for implementing a reliable placement engine for a block device. The method includes the steps of...
US-9,740,626 Sharing data structures between processes by semi-invasive hybrid approach
Techniques herein are for sharing data structures between processes. A method involves obtaining a current memory segment that begins at a current base address...
US-9,740,625 Selectable address translation mechanisms within a partition
An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to...
US-9,740,624 Selectable address translation mechanisms within a partition
An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to...
US-9,740,623 Object liveness tracking for use in processing device cache
A processing device comprises a processing device cache and a cache controller. The cache controller initiates a cache line eviction process and determines...
US-9,740,622 Extended fuse reprogrammability mechanism
An apparatus includes a semiconductor fuse array, disposed on a semiconductor die, into which is programmed configuration data. The semiconductor fuse array has...
US-9,740,621 Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching,...
Memory controllers employing memory capacity and/or bandwidth compression with next read address prefetching, and related processor-based systems and methods...
US-9,740,620 Distributed history buffer flush and restore handling in a parallel slice design
An approach is provided in which a computing system captures content included in a history buffer entry that corresponds to a flush ITAG. The computing system,...
US-9,740,619 Methods and systems for caching data using behavioral event correlations
A method is disclosed including a client accessing a cache for a value of an object based on an object identification (ID), initiating a request to a cache...
US-9,740,618 Memory nest efficiency with cache demand generation
Embodiments of the disclosure relate to optimizing a memory nest for a workload. Aspects include an operating system determining the cache/memory footprint of...
US-9,740,617 Hardware apparatuses and methods to control cache line coherence
Methods and apparatuses to control cache line coherence are described. A hardware processor may include a first processor core with a cache to store a cache...
US-9,740,616 Multi-granular cache management in multi-processor computing environments
Cache lines in a multi-processor computing environment are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed...
US-9,740,615 Processor directly storing address range of co-processor memory accesses in a transactional memory where...
Monitoring, by a processor having a cache, addresses accessed by a co-processor associated with the processor during transactional execution of a transaction by...
US-9,740,614 Processor directly storing address range of co-processor memory accesses in a transactional memory where...
Monitoring, by a processor having a cache, addresses accessed by a co-processor associated with the processor during transactional execution of a transaction by...
US-9,740,613 Cache memory system and processor system
A cache memory system has a first cache memory comprising one or more levels, to store data corresponding to addresses, a second cache memory comprising a...
US-9,740,612 Systems and methods for maintaining the coherency of a store coalescing cache and a load cache
A method for maintaining the coherency of a store coalescing cache and a load cache is disclosed. As a part of the method, responsive to a write-back of an...
US-9,740,611 Memory management for graphics processing unit workloads
A method, a device, and a non-transitory computer readable medium for performing memory management in a graphics processing unit are presented. Hints about the...
US-9,740,610 Polarity based data transfer function for volatile memory
Apparatus, systems, and methods to implement polarity based data transfer function on a write data unit are described. The transfer function takes into account...
US-9,740,609 Garbage collection techniques for a data storage system
A technique for garbage collection in a data storage system includes determining a dirty physical byte count for each of a plurality of candidate garbage...
US-9,740,608 Garbage collection and other management of memory heaps
A memory heap management facility is provided that is able to perform various management tasks, including, but not limited to, garbage collection, compaction,...
US-9,740,607 Swap operations in memory
Examples of the present disclosure provide apparatuses and methods related to performing swap operations in a memory. An example apparatus might include a first...
US-9,740,606 Reliable distributed messaging using non-volatile system memory
Methods and apparatus for reliable distributed messaging are described. A computer system includes a system memory coupled to one or more processors. The system...
US-9,740,605 Reducing page invalidation broadcasts in virtual storage management
Technical solutions for reducing page invalidation broadcasts in virtual storage management are described. One general aspect includes a method including...
US-9,740,604 Method for allocating storage space using buddy allocator
Provided herein a method for allocating storage space using a buddy allocator, the method including receiving, by a buddy allocator, a block allocation request...
US-9,740,603 Managing content in persistent memory modules when organization of the persistent memory modules changes
Techniques for managing content stored on persistent memory modules so as to ensure that the content can be accessed from the persistent memory modules in the...
US-9,740,602 Memory orprating method and memory device using the same
An operating method for a memory, the memory comprising at least one memory block including a plurality of first pages and a plurality of second pages...
US-9,740,601 Globalization testing management service configuration
Disclosed aspects may include examining a set of product development data of a product development environment. In response to the examining, a set of...
US-9,740,600 Method and device for improving software performance testing
Embodiments of the present disclosure disclose a method and a device for improving software performance testing. The method comprises receiving input data from...
US-9,740,599 Directed random sequence generation method and apparatus for testing software
A verification apparatus and method are disclosed for testing a device or system which is operable in a number of states through which it can transition in a...
US-9,740,598 Live testing of applications based upon a debug keystore
Technologies are disclosed herein for providing live testing of applications based upon a debug keystore. An application developer develops an application and...
US-9,740,597 Transactional execution of native methods
Approaches for more efficiently executing calls to native code from within a managed execution environment are described. The techniques involve attempting to...
US-9,740,596 Method of accelerated test automation through unified test workflows
Various embodiments are describe techniques, methods, and system disclosing accelerated test automation that is invoking a first script representing a first...
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