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Patent # Description
US-9,741,879 SPAD photodiode covered with a network
The invention relates to a single-photon avalanche diode (SPAD) photodiode having a layer made of semiconductor material, including an N doped zone and a P...
US-9,741,875 Sensor chip package structure and manufacturing method thereof
A sensor chip package structure and a manufacturing method thereof are provided. The sensor chip package structure includes a substrate, a sensor chip and a...
US-9,741,873 Avalanche-rugged silicon carbide (SiC) power Schottky rectifier
In at least one general aspect, a SiC device can include a drift region of a first conductivity type, a shielding body, and a Schottky region. The SiC device...
US-9,741,870 Systems and methods for CMOS-integrated junction field effect transistors for dense and low-noise bioelectronic...
A complementary metal oxide semiconductor (CMOS)-integrated junction field effect transistor (JFET) has reduced scale and reduced noise. An exemplary JFET has a...
US-9,741,869 Semiconductor device and method for manufacturing same
A semiconductor device includes a semiconductor substrate including a main surface, an element separation film formed over the main surface, and a fin...
US-9,741,868 Self-aligned split gate flash memory
The present disclosure relates to a self-aligned split gate memory cell, and an associated method. The self-aligned split gate memory cell has a memory gate...
US-9,741,867 Semiconductor device
An object is to achieve low power consumption and a long lifetime of a semiconductor device having a wireless communication function. The object can be achieved...
US-9,741,866 Semiconductor device
To provide a highly reliable semiconductor device which includes a transistor including an oxide semiconductor, in a semiconductor device including a staggered...
US-9,741,865 Method of forming semiconductor device including oxide semiconductor stack with different ratio of indium and...
A highly reliable semiconductor device including an oxide semiconductor is provided by preventing a change in its electrical characteristics. A semiconductor...
US-9,741,864 Thin-film transistor and method for manufacturing same
The present invention provides a thin-film transistor in which transistor characteristics such as drain current and threshold voltage are improved, and a method...
US-9,741,862 Thin film transistor and manufacturing method thereof
A thin film transistor (TFT) includes a gate, a gate insulation layer, a channel, a source, and a drain. The gate is formed on a substrate. The gate insulation...
US-9,741,861 Display device and method for manufacturing the same
A display device and a method for manufacturing the same having a thin film transistor (TFT) including a gate connected to a gate line, a drain connected to a...
US-9,741,860 Semiconductor device
A semiconductor device includes a gate electrode, a gate insulating film which includes oxidized material containing silicon and covers the gate electrode, an...
US-9,741,859 Semiconductor device with graphene layer as channel
A field effect transistor (FET) with a graphene layer as a channel layer is disclosed. The FET provides two gate electrodes, one of which receives the gate...
US-9,741,858 Amorphous silicon semiconductor TFT backboard structure
The present invention provides an amorphous silicon semiconductor TFT backboard structure, which includes a semiconductor layer (4) that has a multi-layer...
US-9,741,857 Approach for an area-efficient and scalable CMOS performance based on advanced Silicon-On-Insulator (SOI),...
New, distinct, and useful architectures for single-legged SOI-MOS were established and fabricated for the very first time. They incorporated into their...
US-9,741,856 Stress retention in fins of fin field-effect transistors
Embodiments of the present invention provide a structure and method of minimizing stress relaxation during fin formation. Embodiments may involve forming a...
US-9,741,855 Semiconductor devices including a stressor in a recess and methods of forming the same
Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast...
US-9,741,854 Method for manufacturing semiconductor device
There is provided a method for manufacturing a semiconductor device including a substrate including a plurality of active regions, a plurality of gate...
US-9,741,853 Stress memorization techniques for transistor devices
Disclosed are methods for stress memorization techniques and transistor devices prepared by such methods. In one illustrative embodiment, the present disclosure...
US-9,741,852 Manufacturing method of semiconductor structure
A manufacturing method of a semiconductor structure is provided. The manufacturing method of the semiconductor structure includes the following steps: providing...
US-9,741,851 Trench junction barrier controlled Schottky
A method for manufacturing a Schottky diode comprising steps of 1) providing a region with a dopant of a second conductivity type opposite to a first...
US-9,741,850 Semiconductor device and method for forming the same
A semiconductor device having a substrate, a gate electrode, a source and a drain, and a buried gate dielectric layer is disclosed. The buried gate dielectric...
US-9,741,849 Integrated circuits resistant to electrostatic discharge and methods for producing the same
Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a heavily doped...
US-9,741,848 Multi-gate tunnel field-effect transistor (TFET)
A Tunnel Field-Effect Transistor (TFET) is provided comprising a source-channel-drain structure of a semiconducting material. The source-channel-drain structure...
US-9,741,847 Methods of forming a contact structure for a vertical channel semiconductor device and the resulting device
One illustrative method disclosed includes, among other things, forming a vertically oriented semiconductor structure above a doped well region defined in a...
US-9,741,846 Semiconductor device
A semiconductor device includes a lateral transistor having: a semiconductor substrate including a drift layer; a first impurity layer in the drift layer; a...
US-9,741,845 Lateral high voltage transistor
A device and a method for forming a device are disclosed. The device includes a substrate with a high voltage (HV) device region. The HV device region is...
US-9,741,844 Lateral double-diffused MOS transistor having deeper drain region than source region
Provided is a semiconductor power device. The semiconductor power device includes a well disposed in a substrate, a gate overlapping the well, a source region...
US-9,741,843 Semiconductor device
A semiconductor device in which current sensing accuracy is maintained while ruggedness of a current sensing region is improved. The semiconductor device...
US-9,741,842 Vertical power transistor device
A power metal-oxide-semiconductor field-effect transistor (MOSFET) includes a substrate, a drift layer over the substrate, and a spreading layer over the drift...
US-9,741,841 Group III-V semiconductor device with strain-relieving layers
According to one exemplary embodiment, a group III-V semiconductor device includes at least one transition layer situated over a substrate. The group III-V...
US-9,741,840 Electronic device including a multiple channel HEMT and an insulated gate electrode
An electronic device can include a lower channel layer, an upper channel layer overlying the lower channel layer and having an opening extending through the...
US-9,741,839 Gate structure of thyristor
A thyristor device that can include a disc-shaped device comprising a semiconductor material forming alternating p-n-p-n type layers. The device can include a...
US-9,741,838 Semiconductor device
A semiconductor device includes a plurality of gate electrodes. Each gate electrode includes a first portion extending from a first end to a second end and a...
US-9,741,837 Bidirectional insulated gate bipolar transistor
A bidirectional IGBT device, including a cellular structure including: two MOS structures, a substrate drift layer, two highly doped buried layers operating for...
US-9,741,836 Semiconductor device and method for driving same
A semiconductor device according to an embodiment includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second...
US-9,741,835 Semiconductor device and insulated gate bipolar transistor with transistor cells and sensor cell
A transistor cell region of a semiconductor device includes transistor cells that are electrically connected to a first load electrode. An idle region includes...
US-9,741,834 Heterojunction bipolar transistor architecture
A transistor includes a sub-collector, a base, a collector between the sub-collector and the base, and an emitter on the base opposite the collector. The...
US-9,741,832 Tunneling field effect transistors with a variable bandgap channel
Tunneling field effect transistors (TFETs) including a variable bandgap channel are described. In some embodiments, one or more bandgap characteristics of the...
US-9,741,831 FinFET and method for manufacturing the same
A method for manufacturing a FinFET, and FinFETs are provided. In various embodiments, the method for manufacturing a FinFET includes forming a fin structure...
US-9,741,830 Method for forming metal oxide semiconductor device
The present invention provides a method of forming a metal oxide semiconductor (MOS) device comprising a gate structure and an epitaxial structure. The gate...
US-9,741,829 Semiconductor device and manufacturing method thereof
A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure,...
US-9,741,828 Mask, manufacturing method thereof and manufacturing method of a thin film transistor
The present invention discloses a mask, a manufacturing method thereof and a manufacturing method of a thin film transistor. The mask includes: a first...
US-9,741,827 Etchant and method of manufacturing display device by using the same
An etchant composition is provided comprising a persulfate from 0.5 to 20 wt %; a fluoride compound from 0.01 to 2 wt %; an inorganic acid from 1 to 10 wt %; a...
US-9,741,826 Transistor structure
A transistor structure including a substrate, a gate, a first dielectric layer, a first contact and a second contact is provided. The gate is disposed on the...
US-9,741,825 Method for manufacturing field effect transistor having widened trench
A method for manufacturing a field effect transistor having a widened trench forms sequentially an epitaxial layer, a trench, an oxidation layer, a...
US-9,741,824 Semiconductor device and fabrication method thereof
The present disclosure provides a method for forming a semiconductor device. The method includes providing a semiconductor substrate; forming a gate structure...
US-9,741,823 Fin cut during replacement gate formation
A method is presented for forming a semiconductor structure. The method includes forming a plurality of vertical fins over a semiconductor layer formed over a...
US-9,741,822 Simplified gate stack process to improve dual channel CMOS performance
A semiconductor device and method of making the same wherein the semiconductor device includes a pFET region including a SiGe channel having a Si-rich top...
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