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Patent # Description
US-9,741,768 Controlling memory cell size in three dimensional nonvolatile memory
A method is provided that includes forming a vertical bit line disposed in a first direction above a substrate, forming a multi-layer word line disposed in a...
US-9,741,767 Electronic device
Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a vertical electrode formed over a substrate; a...
US-9,741,766 Memory device
According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided...
US-9,741,765 Monolithically integrated resistive memory using integrated-circuit foundry compatible processes
Provided is a monolithic integration of resistive memory with complementary metal oxide semiconductor using integrated circuit foundry processes. A memory...
US-9,741,764 Memory device including ovonic threshold switch adjusting threshold voltage thereof
A memory device may include a substrate, a first conductive line on the substrate and extending in a first direction, a second conductive line over the first...
US-9,741,763 Optoelectronic device
An optoelectronic device includes a substrate having a first side, a second side opposite to the first side; a first optoelectronic unit formed on the first...
US-9,741,762 Semiconductor devices and methods for forming patterned radiation blocking on a semiconductor device
Several embodiments for semiconductor devices and methods for forming semiconductor devices are disclosed herein. One embodiment is directed to a method for...
US-9,741,761 Photosensitive imaging devices and associated methods
A monolithic sensor for detecting infrared and visible light according to an example includes a semiconductor substrate and a semiconductor layer coupled to the...
US-9,741,760 Solid-state imaging device with suppression of color mixture, manufacturing method thereof, and electronic...
A solid-state imaging device having a backside illuminated structure, includes: a pixel region in which pixels each having a photoelectric conversion portion...
US-9,741,759 Image sensor and method of manufacturing the same
Image sensor and method of manufacturing the same are provided. The image sensor includes a semiconductor substrate including a pixel area, a voltage connection...
US-9,741,758 Methods of forming image sensors including deposited negative fixed charge layers on photoelectric conversion...
A method of forming an image sensor can be provided by forming a respective photoelectric conversion region in each of a plurality of unit pixel regions of a...
US-9,741,757 Solid-state imaging device with layered microlenses and method for manufacturing same
A solid-state imaging device includes: a first lens layer; and a second lens layer, wherein the second lens layer is formed at least at a periphery of each...
US-9,741,756 Image sensor including planar boundary between optical black and active pixel sensor areas
An image sensor includes a substrate including a sensor array area, a pad area, and a circuit area, a wiring layer on the pad area, and a light-shielding...
US-9,741,755 Physical layout and structure of RGBZ pixel cell unit for RGBZ image sensor
An image sensor is described having a pixel cell unit. The pixel cell unit has first, second and third transfer gate transistor gates on a semiconductor surface...
US-9,741,754 Charge transfer circuit with storage nodes in image sensors
Apparatuses and methods for charge transfer in image sensors are disclosed. One example of an image sensor pixel may include a first charge storage node and a...
US-9,741,753 Array substrate and manufacturing method thereof, and display apparatus thereof
An embodiment of the present disclosure provides an array substrate and a manufacturing method thereof and a display apparatus. The array substrate includes a...
US-9,741,752 Method for manufacturing TFT substrate
Disclosed is a method for manufacturing a TFT substrate, which uses one partial transmitting mask to form patterns of an active layer, a gate insulation layer,...
US-9,741,751 Array substrate fabricating method
The present invention provides an array substrate fabricating method. The array substrate fabricating method comprises the steps of: forming a semiconductor...
US-9,741,750 Thin film transistor, pixel structure, and method for manufacturing the same, array substrate and display device
A thin film transistor, a pixel structure, an array substrate, a display device, a method for manufacturing a thin film transistor, and a method for...
US-9,741,749 Digital circuit having correcting circuit and electronic apparatus thereof
Provided is a digital circuit (30) that comprises: a switching circuit (31) having first transistors (32, 33) supplied with power supply potentials (VDD, VSS);...
US-9,741,748 Thin film transistor array panel and manufacturing method thereof
A thin film transistor array panel includes a substrate, a gate line and a gate pad disposed on the substrate, a gate insulating layer disposed on the gate line...
US-9,741,747 Display panel including static electricity preventing pattern and display device having the same
A display device comprising a display panel that includes an active area, the active area including a data line positioned on a substrate in a first direction...
US-9,741,746 Array substrate, manufacturing method thereof and display device
An array substrate, a manufacturing method thereof and a display device are provided. The array substrate comprises a plurality of gate lines (102) and a...
US-9,741,745 Array substrate, method for manufacturing the same and display device
The present disclosure discloses an array substrate including a display area and a data lead area. The display area includes data signal lines and gate lines....
US-9,741,744 Array substrate, method for manufacturing the same, and display device
An array substrate comprises a TFT, a data line, a gate line and a passivation layer covering the TFT, the data line and the gate line. The array substrate...
US-9,741,743 Array substrate and fabrication method thereof, display panel and display device
Embodiments of the present invention disclose an array substrate comprising: a base substrate, a gate line and a gate electrode located on the base substrate;...
US-9,741,742 Deformable electronic device and methods of providing and using deformable electronic device
Some embodiments include a method of providing an electronic device. The method includes: (i) providing a carrier substrate, (ii) providing a device substrate...
US-9,741,741 Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including...
An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells...
US-9,741,740 Semiconductor device
A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region...
US-9,741,739 Semiconductor manufacturing method and semiconductor device
A semiconductor manufacturing method includes alternately stacking first films and second films to form a stack film. The method includes forming a plurality of...
US-9,741,738 Non-volatile semiconductor storage device and method of manufacturing the same
A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected...
US-9,741,737 Integrated structures comprising vertical channel material and having conductively-doped semiconductor material...
Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower...
US-9,741,736 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, and a first interconnect....
US-9,741,735 Vertical memory devices having charge storage layers with thinned portions
A semiconductor device includes a stack comprising insulating patterns vertically stacked on a substrate and gate patterns interposed between the insulating...
US-9,741,734 Memory devices and systems having reduced bit line to drain select gate shorting and associated methods
3D NAND memory devices and systems having reduced bit line to drain select gate shorting, including associated methods, are provided and described.
US-9,741,733 Three-dimensional semiconductor memory devices
Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The semiconductor devices may include a semiconductor pattern...
US-9,741,732 Integrated structures
Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and ...
US-9,741,731 Three dimensional stacked semiconductor structure
A 3D stacked semiconductor structure is provided, comprising a plurality of stacks vertically formed on a substrate and disposed parallel to each other, a...
US-9,741,730 Semiconductor device and method for manufacturing the same
According to one embodiment, the first separation film separates the control electrode, the first insulating layer, the charge storage layer, the intermediate...
US-9,741,729 Nonvolatile memory cells, nonvolatile memory cell arrays including the same, and methods of fabricating the same
Nonvolatile memory devices includes a charge storage element having a MOS capacitor structure and including a control gate terminal connected to a word line and...
US-9,741,728 Method for forming a split-gate flash memory cell device with a low power logic device
A method of manufacturing an embedded flash memory device is provided. A pair of gate stacks are formed spaced over a semiconductor substrate, and including...
US-9,741,727 Semiconductor memory with U-shaped channel
A semiconductor memory with a U-shaped channel comprises: a U-shaped channel region arranged in a semiconductor substrate, a source region, a drain region, a...
US-9,741,726 Non-volatile memory cell and method of manufacture
A memory device includes a capacitor, a tunneling-enhanced device, and a transistor. In accordance with an embodiment, capacitor has first and second electrodes...
US-9,741,725 Semiconductor device
A semiconductor device can be reduced in size. The semiconductor device has a first conductivity type p type well layer extending in the X direction of the main...
US-9,741,724 SRAM well-tie with an uninterrupted grated first poly and first contact patterns in a bit cell array
An integrated circuit containing an SRAM may be formed using one or more periodic photolithographic patterns for elements of the integrated circuit such as...
US-9,741,723 Semiconductor device having shallow trench isolation structure
A semiconductor device is provided, which prevents a case where the widths of word lines become uneven because of a stress developing at the border between a...
US-9,741,722 Dummy gate structure for electrical isolation of a fin DRAM
Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the...
US-9,741,721 Low leakage non-planar access transistor for embedded dynamic random access memory (eDRAM)
Low leakage non-planar access transistors for embedded dynamic random access memory (eDRAM) and methods of fabricating low leakage non-planar access transistors...
US-9,741,720 Higher `K` gate dielectric cap for replacement metal gate (RMG) FINFET devices
A semiconductor structure includes a semiconductor substrate, n-type and p-type FinFETs on the substrate, each of the n-type and the p-type FinFETs include a...
US-9,741,719 Methods, structures, and designs for self-aligning local interconnects used in integrated circuits
An integrated circuit includes a gate electrode level region that includes a plurality of linear-shaped conductive structures. Each of the plurality of...
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