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Patent # Description
US-9,741,718 High voltage CMOS with triple gate oxide
An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in a...
US-9,741,717 FinFETs with controllable and adjustable channel doping
A method of forming features of a finFET structure includes forming fins on a surface of a substrate. A first liner is formed around each fin and a shallow...
US-9,741,716 Forming vertical and horizontal field effect transistors on the same substrate
A method of forming a vertical FET device and a horizontal FINFET device on a common semiconductor substrate includes forming, on the semiconductor substrate,...
US-9,741,715 Structure to prevent lateral epitaxial growth in semiconductor devices
A semiconductor device includes a set of fin structures having a set of fin ends at a respective vertical surface of a fin structure and is separated by a set...
US-9,741,714 Inductor structure
An inductor structure includes a first inductor and a second inductor. The second inductor includes a loop that surrounds the first inductor. The first inductor...
US-9,741,713 Parasitic lateral bipolar transistor with improved ideality and leakage currents
A semiconductor structure includes a semiconductor substrate of n-type or p-type, a well of a type opposite the substrate, the well acting as the base of a...
US-9,741,712 Semiconductor devices with trench gate structures in a semiconductor body with hexagonal crystal lattice
A semiconductor device includes trench gate structures in a semiconductor body with hexagonal crystal lattice. A mean surface plane of a first surface is tilted...
US-9,741,711 Cascode semiconductor device structure and method therefor
In one embodiment, a cascode rectifier structure includes a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor...
US-9,741,710 Electrostatic discharge protection device and method for manufacturing the same, and chip component with the same
An electrostatic discharge protection device includes a base, a plurality of electrodes arranged on the base separated from each other, a function layer...
US-9,741,709 ESD protection device
The present invention is provided with a Si substrate, an ESD protection circuit formed in the Si substrate, pads formed on the surface of the Si substrate and...
US-9,741,708 Transient voltage suppressor and ESD protection device and array thereof
Provided is a transient voltage suppressor including a substrate, a well region of a first conductivity type, a first doped region of a second conductivity...
US-9,741,707 Immunity to inline charging damage in circuit designs
Approaches for checking a design of an integrated circuit using an antenna rule are provided. A method includes determining a figure of merit for a transistor...
US-9,741,706 Immunity to inline charging damage in circuit designs
Approaches for checking a design of an integrated circuit using an antenna rule are provided. A method includes determining a figure of merit for a transistor...
US-9,741,704 Silicon-controlled rectifier and an ESD clamp circuit
A silicon-controlled rectifier (SCR) includes a first-type field, a second-type first field and a second-type second field disconnectedly formed in a first-type...
US-9,741,703 Integrated circuit containing standard logic cells and ilbrary-compatible, NCEM-enabled fill cells, including...
An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells...
US-9,741,702 Semiconductor power modules and devices
An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive...
US-9,741,701 Method of manufacturing a package-on-package type semiconductor package
A method for manufacturing a semiconductor package, for example a package-on-package type semiconductor device package. As non-limiting examples, various...
US-9,741,700 Lighting device
The present disclosure provides a lighting device comprising: a reflective element layer; an optical resin layer formed on the reflective element layer; a...
US-9,741,699 Light emitting device
The present invention relates to a light emitting device comprising a transparent substrate which light can pass through and at least one LED chip emitting...
US-9,741,698 Light-emitting device
A light-emitting device includes a substrate, a first light-emitting element mounted on the substrate, an annular transparent dam formed on the substrate so as...
US-9,741,697 Three-dimensional 3D-oP-based package
The present invention discloses a three-dimensional 3D-oP (three-dimensional offset-printed memory)-based package (3D.sup.2-oP). The mask-patterns for different...
US-9,741,696 Thermal vias disposed in a substrate proximate to a well thereof
An apparatus relates generally to a three-dimensional stacked integrated circuit. In such an apparatus, the three-dimensional stacked integrated circuit has at...
US-9,741,695 Three-dimensional hybrid packaging with through-silicon-vias and tape-automated-bonding
A 3-dimensional hybrid package including an integrated circuit chip stack formed on a laminate, the integrated chip stack further including a first chip and a...
US-9,741,694 Semiconductor structure and method of manufacturing the same
A semiconductor structure and a method for forming the same are provided. The method comprises: providing a first semiconductor workpiece; bonding a second...
US-9,741,693 Semiconductor package and method of forming the same
The present disclosure provides a semiconductor package, including a first device having a first joining surface, a first conductive component at least...
US-9,741,692 Methods to form high density through-mold interconnections
Methods of fabricating a microelectronic device comprising forming a microelectronic substrate having a plurality microelectronic device attachment bond pads...
US-9,741,691 Power delivery network (PDN) design for monolithic three-dimensional (3-D) integrated circuit (IC)
Systems and methods relate to power delivery networks (PDNs) for monolithic three-dimensional integrated circuits (3D-ICs). A monolithic 3D-IC includes a first...
US-9,741,690 Redistribution layers in semiconductor packages and methods of forming same
An embodiment package includes a first integrated circuit die, an encapsulent around the first integrated circuit die, and a conductive line electrically...
US-9,741,689 3-D package having plurality of substrates
A package includes an interposer, which includes a first substrate free from through-vias therein, redistribution lines over the first substrate, and a first...
US-9,741,688 Method for manufacturing a semiconductor device
A link device with a large density routing is attached to a package in order to provide a high-density interconnect pathway to interconnect semiconductor...
US-9,741,687 Integrated circuit structure with active and passive devices in different tiers
An integrated circuit structure includes a two-tier die including a first tier and a second tier over and bonded to the first tier. The first tier includes a...
US-9,741,686 Electronic package and method of connecting a first die to a second die to form an electronic package
Some embodiments relate to an electronic package. The electronic package includes a substrate that includes a plurality of buildup layers. A first die is...
US-9,741,685 Methods for directly bonding silicon to silicon or silicon carbide to silicon carbide
A method for bonding a first silicon part to a second silicon part includes arranging the first silicon part and the second silicon part in direct physical...
US-9,741,684 Wafer bonding edge protection using double patterning with edge exposure
Wafer bonding edge protection techniques are provided. In one aspect, a method of forming Cu interconnects in a wafer includes: forming a dielectric layer on...
US-9,741,683 Device packaging facility and method, and device processing apparatus utilizing phthalate
Provided are a device packing facility and method using phthalate and a device processing apparatus utilizing the phthalate. The device packaging facility...
US-9,741,682 Structures to enable a full intermetallic interconnect
A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder...
US-9,741,681 Debonding schemes
An apparatus includes a bottom stage configured to hold a bottom surface of a substrate stack including at least two substrates, a top stage configured to hold...
US-9,741,680 Wire bond through-via structure and method
A stackable integrated circuit chip layer and module device that avoids the use of electrically conductive elements on the external surfaces of a layer...
US-9,741,678 Laser welding machine and laser welding method using the same
A laser welding machine includes: an elevator that is capable of sliding an elevating platform; a pressing actuator that is fixed to the elevating platform at a...
US-9,741,677 Semiconductor device including antistatic die attach material
A semiconductor device includes a substrate, a semiconductor die, and an antistatic die attach material between the substrate and the semiconductor die. The...
US-9,741,676 Tin-indium based low temperature solder alloy
A lead-free solder alloy having a low melting temperature and low yield strength is disclosed. The solder alloy includes 5.0-20.0 wt. % of indium (In), 1.0-5.0...
US-9,741,675 Bump structures, semiconductor device and semiconductor device package having the same
The present disclosure relates to bump structures and a semiconductor device and semiconductor device package having the same. The semiconductor device includes...
US-9,741,674 Semiconductor device
A semiconductor device includes a semiconductor substrate in which a through hole is formed, a transistor formed on the upper surface side of the semiconductor...
US-9,741,673 RF transistor packages with high frequency stabilization features and methods of forming RF transistor packages...
A packaged RF transistor device includes an RF transistor die including a plurality of RF transistor cells, an RF input lead coupled to the plurality of RF...
US-9,741,672 Preventing unauthorized use of integrated circuits for radiation-hard applications
An integrated circuit, a method of forming an integrated circuit, and a semiconductor are disclosed for preventing unauthorized use in radiation-hard...
US-9,741,671 Semiconductor die with backside protection
A semiconductor die with backside protection includes an active region and a first polysilicon layer formed on a front side of a semiconductor substrate. A...
US-9,741,670 Electronic chip comprising multiple layers for protecting a rear face
An electronic chip and a method of making thereof is provided, where the electronic chip includes at least: an electronic circuit arranged at a front face of a...
US-9,741,669 Forming large chips through stitching
A method includes performing a first light-exposure and a second a second light-exposure on a photo resist. The first light-exposure is performed using a first...
US-9,741,668 Semiconductor packages having residual stress layers and methods of fabricating the same
A semiconductor package is provided. The semiconductor includes a lower package and an upper package stacked on the lower package. The lower package includes a...
US-9,741,667 Integrated circuit with die edge assurance structure
Integrated circuits with edge assurance structures are provided for more reliable and efficient monitoring of the die edge integrity using, for example,...
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