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Patent # Description
US-9,761,730 Imaging device and electronic device
An imaging device that does not need a lens is provided. The imaging device includes a first layer, a second layer, and a third layer. The second layer is...
US-9,761,729 TFT switch and method for manufacturing the same
A thin-film transistor (TFT) switch includes a gate, a drain, a source, a semiconductor layer, and a fourth electrode. The drain is connected to a first signal....
US-9,761,728 Self-aligned source/drain junction for vertical field-effect transistor (FET) and method of forming the same
A method for manufacturing a semiconductor device includes forming a bottom source/drain region on a substrate, forming a semiconductor layer on the bottom...
US-9,761,727 Vertical FETs with variable bottom spacer recess
A method of forming a variable spacer in a vertical transistor device includes forming a first source/drain of a first transistor on a substrate; forming a...
US-9,761,726 Vertical field effect transistor with undercut buried insulating layer to improve contact resistance
Semiconductor devices having vertical field effect transistor (FET) devices with reduced contact resistance are provided, as well as methods for fabricating...
US-9,761,725 Thin film transistor display device with zinc nitride ohmic contact layer
Embodiments of the present invention relates to a thin film transistor and a method for manufacturing the same, a display substrate and a display device. The...
US-9,761,724 Semiconductor device structures and methods of forming semiconductor structures
A method of patterning a semiconductor film is described. According to an embodiment of the present invention, a hard mask material is formed on a silicon film...
US-9,761,723 Structure and formation method of finFET device
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a...
US-9,761,722 Isolation of bulk FET devices with embedded stressors
A field-effect transistor device and a method of isolating a field-effect transistor device. The method includes forming a layer of silicon germanium (SiGe)...
US-9,761,721 Field effect transistors with self-aligned extension portions of epitaxial active regions
A gate structure is formed across a single crystalline semiconductor fin. An amorphizing ion implantation is performed employing the gate structure as an...
US-9,761,720 Replacement body FinFET for improved junction profile with gate self-aligned junctions
After forming an epitaxial semiconductor layer on portions of a semiconductor located on opposite sides of a sacrificial gate structure, dopants from the...
US-9,761,719 Semiconductor device having silicon-germanium source/drain regions with varying germanium concentrations
A semiconductor device may include: a semiconductor substrate, a device isolating layer embedded within the semiconductor substrate and defining an active...
US-9,761,718 Semiconductor device and method for manufacturing same
A semiconductor device includes: a sidewall insulating film; a gate electrode; source and drain regions; a first stress film; and a second stress film.
US-9,761,717 Stress memorization technique for strain coupling enhancement in bulk finFET device
A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the...
US-9,761,716 Semiconductor device and fabrication method thereof
The present disclosure provides semiconductor devices and fabrication methods thereof. A stacked substrate includes an insulating layer between a substrate and...
US-9,761,715 Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row...
A ferroelectric field effect transistor comprises a semiconductive channel comprising opposing sidewalls and an elevationally outermost top. A source/drain...
US-9,761,714 Semiconductor device
A field oxide film lies extending from the underpart of a gate electrode to a drain region. A plurality of projection parts projects from the side face of the...
US-9,761,713 Multi-threshold voltage devices and associated techniques and configurations
Embodiments of the present disclosure describe multi-threshold voltage devices and associated techniques and configurations. In one embodiment, an apparatus...
US-9,761,712 Vertical transistors with merged active area regions
A method for device layout with vertical transistors includes identifying active area regions in a layout of a semiconductor device with vertical transistors....
US-9,761,711 Semiconductor device
A semiconductor device includes a first electrode, a second electrode, a first semiconductor region of a first conductivity type that is between the first...
US-9,761,710 Vertical-channel semiconductor device
A vertical-channel semiconductor device having a buried bit line is disclosed. The vertical-channel semiconductor device enables an active pillar including a...
US-9,761,709 III-nitride transistor with enhanced doping in base layer
A vertical trench MOSFET comprising: a N-doped substrate of a III-N material; and an epitaxial layer of the III-N material grown on a top surface of the...
US-9,761,708 Method of manufacturing semiconductor device and semiconductor device
A semiconductor device includes a supporting substrate, an insulating film formed in a first region over the supporting substrate, a first semiconductor layer...
US-9,761,707 Laterally diffused MOSFET with isolation region
A device formed in a semiconductor substrate is disclosed. The device include a core device formed in the semiconductor substrate, a first deep trench isolation...
US-9,761,706 SiC trench transistor and method for its manufacture
An SiC trench transistor having a first terminal and an epitaxial layer positioned vertically between a gate trench and a second terminal; a compensation layer...
US-9,761,705 Wide band gap semiconductor device
A semiconductor device comprises an n+ type SiC semiconductor substrate, an n type low concentration drift layer of an SiC semiconductor on the substrate, p...
US-9,761,704 Heterostructure power transistor with AlSiN passivation layer
A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron...
US-9,761,703 Wide bandgap semiconductor device with adjustable voltage level
A wide bandgap semiconductor device with an adjustable voltage level includes a wide bandgap semiconductor power unit and a level adjusting unit. The wide...
US-9,761,702 Power MOSFET having planar channel, vertical current path, and top drain electrode
In one embodiment, a power MOSFET cell includes an N+ silicon substrate having a drain electrode. An N-type drift layer is grown over the substrate. An N-type...
US-9,761,700 Bipolar transistor on high-resistivity substrate
Systems and methods are disclosed for processing radio frequency (RF) signals using one or more bipolar transistors disposed on or above a high-resistivity...
US-9,761,699 Integration of strained silicon germanium PFET device and silicon NFET device for finFET structures
A method of forming a finFET transistor device includes forming a crystalline, compressive strained silicon germanium (cSiGe) layer over a substrate; masking a...
US-9,761,698 Air gap contact formation for reducing parasitic capacitance
A functional gate structure is located on a surface of a semiconductor material portion and including a U-shaped gate dielectric portion and a gate conductor...
US-9,761,697 Semiconductor device and method for fabricating the same
A semiconductor device comprises a substrate, a gate structure and a gate spacer. The substrate has a semiconductor fin protruding from a surface of the...
US-9,761,696 Self-aligned trench MOSFET and method of manufacture
A trench metal-oxide-semiconductor field effect transistor (MOSFET), in accordance with one embodiment, includes a drain region, a plurality of gate regions...
US-9,761,695 Method for fabricating a shield gate trench MOSFET
A method for fabricating a shield gate trench MOSFET, including the following steps: forming a hard mask layer and defining a gate forming region; forming a top...
US-9,761,694 Vertical FET with selective atomic layer deposition gate
Vertical channel field effect transistors and methods of forming the same include forming one or more vertical channels on a bottom source/drain layer. A seed...
US-9,761,693 Method for fabricating semiconductor device
A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a gate structure is formed on the substrate, a spacer is formed...
US-9,761,692 Method of using polysilicon as stop layer in a replacement metal gate process
A method for fabricating semiconductor device preferably forms a stop layer composed of amorphous silicon between a first BM layer and a second BBM layer of one...
US-9,761,691 Integrated circuits including replacement gate structures and methods for fabricating the same
Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes...
US-9,761,690 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming an interfacial layer on the...
US-9,761,689 Method of forming a semiconductor device and according semiconductor device
The present disclosure provides a method of forming a semiconductor device, including a shaping of a gate structure of the semiconductor device such that a...
US-9,761,688 Method of fabricating semiconductor device with tilted preamorphized implant
A method for fabricating a semiconductor device may include: preparing a semiconductor substrate including a doping region; performing tilt implantation using a...
US-9,761,687 Method of forming gate dielectric layer for MOS transistor
A method of forming a gate dielectric layer for a MOS transistor includes the following steps. A gate dielectric layer is formed on a substrate. A nitridation...
US-9,761,686 Semiconductor wafer, method of producing semiconductor wafer, and heterojunction bipolar transistor
Techniques are provided that can impart sufficient electrical conductivity to a semiconductor crystal exhibiting low doping efficiency for silicon atoms, such...
US-9,761,685 Manufacturing method for semiconductor device
Provided is a method for manufacturing a semiconductor device that improves the reliability of the semiconductor device. An opening is formed in an insulating...
US-9,761,684 Method and structure for metal gates
A semiconductor device having metal gates and methods of forming the same are disclosed. The semiconductor device includes a substrate and a gate structure over...
US-9,761,683 Semiconductor device and manufacturing method thereof
A method of manufacturing a Fin FET includes forming a fin structure including an upper layer. Part of the upper layer is exposed from an isolation insulating...
US-9,761,682 Semiconductor device with silicon nitride film on nitride semiconductor layer and manufacturing method thereof
In order to improve the characteristics of a semiconductor device including: a channel layer and a barrier layer formed above a substrate; and a gate electrode...
US-9,761,681 Semiconductor device
The semiconductor device includes a gate insulation film covering inner surfaces of the first trench and the second trench, and an inner surface of an...
US-9,761,680 Semiconductor device with embedded non-volatile memory and method of fabricating semiconductor device
The present invention provides a semiconductor device, including a substrate with a memory region and a logic region, the substrate having a recess disposed in...
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