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Patent # Description
US-9,761,627 Image sensor and electronic device including the same
An image sensor includes a semiconductor substrate integrated with at least one first photo-sensing device configured to sense light in a blue wavelength region...
US-9,761,626 Solid-state image pickup device
A solid-state image pickup device is provided which can inhibit degradation of image quality which may occur when a global electronic shutter operation is...
US-9,761,625 Image sensor having overlapping exposure regions and pixels with misaligned photodiodes
In a solid state image sensor which has two photodiodes juxtaposed in a predetermined direction in each pixel and is formed by carrying out divided exposure,...
US-9,761,624 Pixels for high performance image sensor
Visual and near infrared pixels may have deep photodiodes to ensure sufficient capture of light. The pixels may have a silicon layer that is etched to form a...
US-9,761,623 Backside illuminated (BSI) image sensor with a reflector
A backside illuminated (BSI) image sensor with a reflector is provided. A pixel sensor is arranged on a lower side of a semiconductor substrate, and comprises a...
US-9,761,622 CMOS image sensor structure with crosstalk improvement
A semiconductor device includes a substrate, a device layer, a composite grid structure, a passivation layer and color filters. The device layer overlies the...
US-9,761,621 Color filter array, imagers and systems having same, and methods of fabrication and use thereof
A pixel cell with a photosensitive region formed in association with a substrate, a color filter formed over the photosensitive region, the color filter...
US-9,761,620 Method and system for manufacturing using a programmable patterning structure
A charge array wafer includes a plurality of electrical charge storage cells disposed in an array configuration. A programmable amount of charge in each of the...
US-9,761,619 Curved image sensor, method for fabricating the same, and electronic device having the same
The curved image sensor may include: a first substrate including a plurality of photoelectric conversion elements and having a curved first surface; a bonding...
US-9,761,618 Solid-state imaging apparatus, method for manufacturing the same, and imaging system
A solid-state imaging apparatus, comprising a first semiconductor region of a first conductivity type provided on a substrate by an epitaxial growth method, a...
US-9,761,617 Method for manufacturing array substrate, array substrate and display device
A method for manufacturing an array substrate comprises: forming a pixel electrode and a gate of a thin film transistor on a substrate; forming a gate...
US-9,761,616 Manufacturing method of array substrate with reduced number of patterning processes array substrate and display...
An array substrate, a manufacturing method thereof and a display device are disclosed. Patterns comprising a gate, a gate insulating layer and a polysilicon...
US-9,761,615 Array substrate, manufacturing method thereof and display device
An array substrate, a manufacturing method thereof and a display device are disclosed. The array substrate comprises: a base substrate (1), thin-film...
US-9,761,614 Thin film transistor array panel and manufacturing method thereof
A thin film transistor array panel is provided. A thin film transistor is positioned on a substrate. A first passivation layer is positioned on the thin film...
US-9,761,613 TFT array substrate and manufacturing method thereof
A thin film transistor (TFT) array substrate is disclosed and having a pixel region and a peripheral region surrounding the pixel region, and the pixel region...
US-9,761,611 Semiconductor device
A semiconductor device includes an oxide layer, a source electrode layer in contact with the oxide layer, a first drain electrode layer in contact with the...
US-9,761,610 Strain release in PFET regions
A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric...
US-9,761,609 Structure having group III-V, Ge and SiGe Fins on insulator
A method provides a first substrate supporting an insulator layer having trenches formed therein; filling the trenches using an epitaxial growth process with at...
US-9,761,608 Lateral bipolar junction transistor with multiple base lengths
A method comprises forming shallow trenches in an intrinsic base semiconductor layer and forming a first base layer thereon; applying a first mask to the layer;...
US-9,761,607 Method for producing strained semi-conductor blocks on the insulating layer of a semi-conductor on insulator...
A method for producing a microelectronic device is provided, including forming on an insulating layer of a semi-conductor on insulator type substrate, a first...
US-9,761,606 Stacked non-volatile semiconductor memory device with buried source line and method of manufacture
According to one embodiment, a semiconductor device includes a first interconnection, a first semiconductor region, a stacked body, a columnar portion, first...
US-9,761,605 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a substrate; a stacked body; a first columnar portion; a second columnar portion; and a...
US-9,761,604 3D vertical NAND with III-V channel
Disclosed herein is 3D memory with vertical NAND strings having a III-V compound channel, as well as methods of fabrication. The III-V compound has at least one...
US-9,761,603 Methods for fabricating a semiconductor device and semiconductor devices fabricated by the same
The inventive concepts provide methods for fabricating a semiconductor device and semiconductor devices fabricated by the same. According to the method,...
US-9,761,602 Semiconductor memory device
A semiconductor memory device to which a Peri Under Cell (PUC) structure is applied is disclosed. The semiconductor memory device includes a word line...
US-9,761,601 Semiconductor memory device and method for manufacturing same
A semiconductor memory device having one embodiment which includes a substrate; a stacked body provided on the substrate and including a plurality of electrode...
US-9,761,600 Semiconductor memory device
A semiconductor device according to an embodiment includes two semiconductor pillars, a connection member connected between the two semiconductor pillars, and a...
US-9,761,599 Integrated structures containing vertically-stacked memory cells
Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory...
US-9,761,598 Programmable logic device (PLD)
To provide a semiconductor device with excellent charge retention characteristics, a transistor including a thick gate insulating film to achieve low leakage...
US-9,761,597 Nonvolatile semiconductor storage device, and method of manufacturing the same nonvolatile semiconductor...
A nonvolatile semiconductor memory includes an electrically data rewritable or erasable memory cell. The memory cell includes a tunnel insulating film provided...
US-9,761,596 Non-volatile memory and manufacturing method thereof
A non-volatile memory having memory cells is provided. The memory cells include stack structures, floating gates, tunneling dielectric layers, erase gate...
US-9,761,595 One-time programming device and a semiconductor device
A one-time programming device includes a field effect semiconductor transistor with a gate or a channel region of the field effect semiconductor transistor...
US-9,761,594 Hardmask for a halo/extension implant of a static random access memory (SRAM) layout
Approaches for providing a hardmask used during a halo/extension implant of a static random access memory (SRAM) layout for a semiconductor device are...
US-9,761,593 Semiconductor device
A semiconductor device includes: a substrate having a plurality of active regions; a plurality of bit lines extending in a first direction, the plurality of bit...
US-9,761,592 Structure and formation method of semiconductor device with embedded capacitor
A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a dielectric layer...
US-9,761,591 Method of forming semiconductor device including edge chip and related device
A method of forming a semiconductor device includes forming a molding layer and a supporter layer on a substrate including an etch stop layer, forming a mask...
US-9,761,590 Passing access line structure in a memory device
A method for memory device fabrication includes forming a plurality of continuous fins on a substrate. An insulator material is formed around the fins. The...
US-9,761,589 Method of operating semiconductor memory device with floating body transistor using silicon controlled...
Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are...
US-9,761,588 Semiconductor device having a wide-gap semiconductor layer in an insulating trench
A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a...
US-9,761,587 Tall strained high percentage silicon germanium fins for CMOS
A silicon germanium alloy (SiGe) fin having a first germanium content is provided within first and second device regions. Each SiGe fin is located on a...
US-9,761,586 Method and structure for FinFET device
The present disclosure describes a fin-like field-effect transistor (FinFET). The device includes one or more fin structures over a substrate, each with...
US-9,761,585 Macro transistor devices
Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to...
US-9,761,584 Buried channel semiconductor device and method for manufacturing the same
A method for manufacturing a semiconductor device includes forming one or more fins extending in a first direction over a substrate. The one or more fins...
US-9,761,583 Manufacturing of self aligned interconnection elements for 3D integrated circuits
A method for making connection elements between two different levels of components in a 3D integrated circuit, including: forming a lateral insulating area...
US-9,761,582 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device comprising: a first electrode; a first semiconductor region of a first conductivity type; a second semiconductor region of a second...
US-9,761,581 Single mask level including a resistor and a through-gate implant
A method of forming an IC includes providing a field dielectric in a portion of a semiconductor surface, a bipolar or Schottky diode (BSD) class device area, a...
US-9,761,580 Methods of forming an array comprising pairs of vertically opposed capacitors and arrays comprising pairs of...
A method of forming an array comprising pairs of vertically opposed capacitors comprises forming an upwardly-open conductive lining in individual capacitor...
US-9,761,579 C-shaped resistor and semiconductor device including the same
A resistor includes a first conductive layer; a second conductive layer protruding from the first conductive layer; a third conductive layer located above and...
US-9,761,578 Display device including electrostatic discharge circuit
The present invention relates to a display device including a static electricity discharge circuit. The display device according to an exemplary embodiment of...
US-9,761,577 Semiconductor device
A semiconductor device includes a power element and a heat sensing element configured to detect a temperature of the power element. The power element includes...
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