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Patent # Description
US-9,761,576 Optoelectronic semiconductor chip and method for fabrication thereof
An optoelectronic semiconductor chip has a first semiconductor layer sequence which comprises a multiplicity of microdiodes, and a second semiconductor layer...
US-9,761,575 Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including...
An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells...
US-9,761,574 Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including...
An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells...
US-9,761,573 Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including...
An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells...
US-9,761,572 Memory device layout, semiconductor device, and method of manufacturing memory device
A layout of a memory device is stored on a non-transitory computer-readable medium. The layout includes a plurality of active area regions, a lowermost...
US-9,761,571 Thermally enhanced fully molded fan-out module
A method of making a semiconductor device can include providing a temporary carrier with adhesive. A first semiconductor die and a second semiconductor die can...
US-9,761,570 Electronic component package with multple electronic components
A method for making an electronic component package from an encapsulated panel. The encapsulated panel includes two packaging substrate assembles including...
US-9,761,569 Leadframe-based system-in-packages having sidewall-mounted surface mount devices and methods for the production...
Embodiments of a method for fabricating System-in-Packages (SiPs) are provided, as are embodiments of a SiP. In one embodiment, the method includes producing a...
US-9,761,568 Thin fan-out multi-chip stacked packages and the method for manufacturing the same
A fan out type multi-chip stacked package includes a chip stacked assembly having a plurality of chips vertically stacked. The electrodes of the chips and one...
US-9,761,567 Power semiconductor module and composite module
A power semiconductor module includes a wiring member that electrically connects a front surface electrode of a semiconductor element and a circuit board of an...
US-9,761,566 Multi-die structure and method of forming same
A method includes forming a semiconductor device comprising a semiconductor die surrounded by a molding material, wherein a contact metal of the semiconductor...
US-9,761,565 Microelectronic packages having embedded sidewall substrates and methods for the producing thereof
Methods for fabricating microelectronic packages and microelectronic packages are provided. In one embodiment, the microelectronic package fabrication method...
US-9,761,564 Layout of transmission vias for memory device
Apparatuses and methods for supplying power to a plurality of dies are described. An example apparatus includes: a substrate; first, second and third memory...
US-9,761,563 Multi-chip package having a stacked plurality of different sized semiconductor chips, and method of...
Provided is a multi-chip package in which a plurality of semiconductor chips having different sizes are stacked. A multi-chip package may include a substrate,...
US-9,761,562 Semiconductor device packages including a controller element
Semiconductor device packages include a stack of semiconductor memory devices positioned over an interposer substrate, a controller element, and a...
US-9,761,561 Edge structure for backgrinding asymmetrical bonded wafer
Semiconductor devices and methods of forming a semiconductor device are disclosed. The device includes a wafer with top and bottom surfaces. The wafer includes...
US-9,761,560 Display device
A display device includes a panel substrate including a pad region, and a COF (Chip On Film) including a wire region, the wire region including a plurality of...
US-9,761,559 Semiconductor package and fabrication method thereof
A semiconductor package includes a first logic die, a second logic die disposed in close proximity to the first logic die, a bridge memory die coupled to both...
US-9,761,557 CMOS-MEMS integration by sequential bonding method
Methods for bonding two wafers are disclosed. In one aspect, a first wafer includes an integrated circuit and the second wafer including a MEMS device. The...
US-9,761,556 Method of manufacturing electronic device
An electronic component mounting device, includes a stage in which a plurality of stage portions are defined, a first heater provided in the plurality of stage...
US-9,761,555 Passive component structure and manufacturing method thereof
A manufacturing method of a passive component structure includes the following steps. A protection layer is formed on a substrate, and bond pads of the...
US-9,761,554 Ball bonding metal wire bond wires to metal pads
An apparatus, and methods therefor, relates generally to an integrated circuit package. In such an apparatus, a platform substrate has a copper pad. An...
US-9,761,553 Inductor with conductive trace
Among other things, an inductor comprising a conductive trace and a method for forming the inductor are provided. The inductor comprises a magnetic structure,...
US-9,761,552 Electronic apparatus and method for fabricating the same
An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and...
US-9,761,551 Solder joint structure for ball grid array in wafer level package
A semiconductor device package and a method for forming the same using an improved solder joint structure are disclosure. The package includes solder joints...
US-9,761,550 Power semiconductor device with a double metal contact and related method
A power semiconductor device that includes a stack of a thin metal layer and a thick metal layer over the active region thereof, and a method for the...
US-9,761,549 Semiconductor device and fabrication method
Semiconductor devices and methods are provided. The semiconductor device can include a semiconductor substrate, a plurality of solder pads disposed on the...
US-9,761,548 Bond pad structure
A bond pad structure includes a first oxide layer that overlies a substrate. A plurality of adhesion structures are formed over the first oxide layer. A second...
US-9,761,547 Crystalline tile
A system and method for vertically integrating heterogeneous devices into a 3D tile architecture are disclosed. The system uses high precision microelectronics...
US-9,761,546 Trap layer substrate stacking technique to improve performance for RF devices
Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating...
US-9,761,545 Isolator and method of manufacturing isolator
An isolator is configured by a transmission circuit, a transformer, and a reception circuit. A first coil of the transformer is disposed on a back surface of a...
US-9,761,544 Semiconductor device
A semiconductor device is provided with: a semiconductor integrated circuit having a bump mounting surface; and a thin-film capacitor portion connected to the...
US-9,761,543 Integrated circuits with thermal isolation and temperature regulation
Integrated circuits with a molded package including a cavity and a semiconductor die spaced from an interior surface of the molded package within the cavity....
US-9,761,542 Liquid metal flip chip devices
Embodiments of the present invention provide an improved method and structure for flip chip implementation. The interconnections between the electronic circuit...
US-9,761,541 Semiconductor device and method of manufacturing the same
A semiconductor device with improved reliability is provided. The semiconductor device is characterized by its embodiments in that sloped portions are formed on...
US-9,761,540 Wafer level package and fabrication method thereof
A semiconductor device that includes a redistribution layer (RDL) is disclosed. A chip is mounted on the RDL within a chip mounting area. The RDL is...
US-9,761,539 Wafer rigidity with reinforcement structure
Reinforcement structures used with a thinned wafer and methods of manufacture are provided. The method includes forming trenches or vias at least partially...
US-9,761,538 Method for making a shielded integrated circuit (IC) package with an electrically conductive polymer layer
A method for making shielded integrated circuit (IC) packages includes providing spaced apart IC dies carried by a substrate and covered by a common...
US-9,761,537 Shielded radio-frequency module having reduced area
Shielded radio-frequency (RF) module having reduced area. In some embodiments, an RF module can include a packaging substrate configured to receive a plurality...
US-9,761,536 Angle referenced lead frame design
A lead frame with an IC chip pad with an alignment notch. A method of mounting a packaged IC chip on a lead frame at a precise angle by aligning a corner of the...
US-9,761,535 Interposer, semiconductor package with the same and method for preparing a semiconductor package with the same
One aspect of the present disclosure provides an interposer for a semiconductor package. The interposer includes a substrate portion and a wall portion disposed...
US-9,761,534 Semiconductor package, semiconductor device using the same and manufacturing method thereof
A semiconductor package includes a package substrate, a first electronic component and a second package body. The package substrate includes a first conductive...
US-9,761,533 Interposer-less stack die interconnect
Techniques for providing a semiconductor assembly having an interconnect die for die-to-die interconnection, an IC package, a method for manufacturing, and a...
US-9,761,532 Hybrid interconnect structure and electronic device employing the same
A hybrid interconnect structure includes a graphene layer between a non-metallic material layer and a metal layer, and a first interfacial bonding layer between...
US-9,761,531 Semiconductor device and method of manufacturing the same
According to one embodiment, a semiconductor device is disclosed. The device includes interconnects each including a catalyst layer and a graphene layer...
US-9,761,530 Graphene wiring and method for manufacturing the same
Graphene wiring of an embodiment has a graphene intercalation compound including a multilayer graphene having graphene sheets stacked therein and an interlayer...
US-9,761,529 Advanced metallization for damage repair
An electrical contact structure for an integrated circuit device is described. A first patterned dielectric layer comprising at least one contact hole, the...
US-9,761,528 Interconnection structure
An interconnection structure fabrication method is provided. The method includes providing a substrate; forming a conductive film with a first thickness and...
US-9,761,527 Semiconductor device
A semiconductor device may include pillars and a plurality of conductive layers being stacked while surrounding the pillars and including a plurality of first...
US-9,761,526 Interconnect structure having tungsten contact copper wiring
Aspects of the present disclosure include interconnect structures for an integrated circuit (IC) structure and methods of making the same. The interconnect...
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