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Patent # Description
US-9,761,525 Multiple back gate transistor
The present disclosure relates to semiconductor structures and, more particularly, to multiple back gate transistor structures and methods of manufacture. The...
US-9,761,524 Metallization of the wafer edge for optimized electroplating performance on resistive substrates
A system for electroless deposition on a substrate is provided, including the following: a chamber; a substrate support configured to receive a substrate having...
US-9,761,523 Interconnect structure with twin boundaries and method for forming the same
A semiconductor device structure with twin-boundaries and method for forming the same are provided. The semiconductor device structure includes a substrate and...
US-9,761,522 Wireless charging package with chip integrated in coil center
A package includes a device die, and an encapsulating material encapsulating the device die therein. The encapsulating material has a top surface coplanar with...
US-9,761,521 Flexible and robust power grid connectivity
Various embodiments provide for flexible and robust power grid connectivity in a server on a chip environment. The power grid has three parallel conductors,...
US-9,761,520 Method of making an electrical connector having electrodeposited terminals
An electrical connectors with electrodeposited terminals that are grown in place by electroplating cavities formed in a series of resist layers. The resist...
US-9,761,519 Package substrate and semiconductor package including the same
A package substrate includes: a body layer; and a pattern layer formed on a surface of the body layer. The pattern layer includes: a wire pattern; a solder pad...
US-9,761,518 Cavity substrate and method of manufacturing the same
A method of manufacturing a cavity substrate of the present invention includes respectively laminating second and third substrates on upper and lower surfaces...
US-9,761,517 Porous alumina templates for electronic packages
Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing...
US-9,761,516 Via and trench filling using injection molded soldering
A method includes forming one or more vias in a substrate, forming a first photoresist layer on a top surface of the substrate and a second photoresist layer on...
US-9,761,515 Substrate structure
A substrate structure includes a dielectric layer, a metal foil, a patterned metal layer, a first patterned solder-resist layer, a release layer and a second...
US-9,761,514 Substrate for integrated circuit devices including multi-layer glass core and methods of making the same
Disclosed are embodiments of a substrate for an integrated circuit (IC) device. The substrate includes a core comprised of two or more discrete glass layers...
US-9,761,513 Method of fabricating three dimensional integrated circuit
A method of fabricating a three dimensional integrated circuit comprises forming a redistribution layer on a first side of a packaging component, forming a...
US-9,761,512 Leadframe assembly, housing assembly, module assembly and method of determining at least one value of a...
A leadframe assembly is formed from an electrically conductive material. The leadframe assembly includes a first longitudinal element, at least one second...
US-9,761,511 Electronic components with integral lead frame and wires
An electronic component includes one or more circuits having electrical connections coupled therewith. The electrical connections include a lead frame as well...
US-9,761,510 Chip package and method for forming the same
A chip package including a first device substrate is provided. The first device substrate is attached to a first surface of a second device substrate. A third...
US-9,761,509 Semiconductor device with throgh-substrate via and method for fabrication the semiconductor device
A method for is used for forming a semiconductor device having a through-substrate via. The method includes providing a preliminary structure having an ILD...
US-9,761,508 Composite heat sink structures
Composite heat sink structures and methods of fabrication are provided, with the composite heat sink structures including: a thermally conductive base having a...
US-9,761,507 Stacked rectifiers in a package
A rectifier package is provided, which comprises a first rectifier die having an anode and a cathode conductively bonded to a first conductive film on a first...
US-9,761,506 Semiconductor device and fabrication method for the same
Provided is a double-sided cooling structure for a semiconductor device using a low processing temperature and reduced processing time utilizing solid phase...
US-9,761,505 Thermal interface material on package
A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes...
US-9,761,504 Passivation structure and method of making the same
A passivation structure includes a bottom dielectric layer. The passivation structure further includes a doped dielectric layer over the bottom dielectric...
US-9,761,503 Packaging mechanisms for dies with different sizes of connectors
Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical...
US-9,761,502 Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with...
An IC includes first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain...
US-9,761,501 Method of manufacturing a semiconductor device and inspecting an electrical characteristic thereof using socket...
Improvement in yield of a semiconductor device is obtained. In addition, increase in service life of a socket terminal is obtained. A projecting portion PJ1 and...
US-9,761,500 FinFET devices having gate dielectric structures with different thicknesses on same semiconductor structure
FinFET devices are formed on the same semiconductor structure wherein at least one finFET device has a gate dielectric structure that is different in thickness...
US-9,761,499 Semiconductor device structure with 110-PFET and 111-NFET current flow direction
A FinFET comprises a hybrid substrate having a top wafer of (100) silicon, a handle wafer of (110) silicon, and a buried oxide layer between the top wafer and...
US-9,761,498 Selective oxidation of buried silicon-germanium to form tensile strained silicon FinFETs
An integrated circuit included n-type FinFETs in an n-region and p-type FinFETs in a p-region. The integrated circuit includes: an n-type fin in the n-region...
US-9,761,497 Techniques and configurations to reduce transistor gate short defects
Embodiments of the present disclosure describe techniques and configurations to reduce transistor gate short defects. In one embodiment, a method includes...
US-9,761,496 Field effect transistor contacts
A method comprises forming a first gate of a first field effect transistor (FET) device over a first channel region of a first fin arranged on a substrate,...
US-9,761,495 Methods of performing concurrent fin and gate cut etch processes for FinFET semiconductor devices and the...
A method includes forming a plurality of fins above a substrate. A plurality of gate structures is formed above the plurality of fins. A first mask layer is...
US-9,761,494 Semiconductor structure and method of forming the same
A semiconductor structure includes a gate structure disposed on a substrate. At least one lightly doped region adjoins the gate structure in the substrate. The...
US-9,761,493 Thin epitaxial silicon carbide wafer fabrication
Techniques for fabricating thin epitaxial SiC device wafers are described. A bulk SiC wafer is used to provide a seed layer of a thin layer of SiC for...
US-9,761,492 Processing method of optical device wafer
A processing method for optical device wafers includes a shielded tunnel forming step and a dividing step. In the shielded tunnel forming step, a sapphire...
US-9,761,491 Self-aligned deep contact for vertical FET
The present disclosure relates to semiconductor structures and, more particularly, to a self-aligned deep contact for a vertical field effect transistor (VFET)...
US-9,761,490 Method for forming contact holes in a semiconductor device
A method for forming a semiconductor device includes forming a device structure having a floating gate, control gate, sidewall spacers, and source and drain...
US-9,761,489 Self-aligned interconnects formed using substractive techniques
A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where...
US-9,761,488 Method for cleaning via of interconnect structure of semiconductor device structure
A method for forming the semiconductor device structure is provided. The method includes forming a metal layer in a first dielectric layer over a substrate and...
US-9,761,486 Method of chip packaging
A method of forming a chip package portion having a reduced loading effect between various metal lines during a leveling process comprises forming a first...
US-9,761,485 Catalyst layer forming method, catalyst layer forming system, and recording medium
A catalyst layer can be uniformly formed on an entire surface of a substrate and an entire inner surface of a recess. A catalyst layer forming method of forming...
US-9,761,484 Interconnect structure and fabrication thereof
Interconnect structures and processes generally include creating point defects in exposed surfaces of the dielectric layer to create a point defect region at a...
US-9,761,483 Semiconductor devices, FinFET devices and methods of forming the same
Semiconductor devices, FinFET devices and methods of forming the same are disclosed. In accordance with some embodiments, a semiconductor device includes a...
US-9,761,482 Enhancement of iso-via reliability
A process of making a semiconductor structure. The process includes forming a wiring line; forming a reliability enhancement material on the wiring line;...
US-9,761,481 Integrated circuits and methods of forming the same with metal layer connection to through-semiconductor via
Integrated circuits and methods of forming integrated circuits are provided herein, in which a plurality of semiconductor devices is formed on a semiconductor...
US-9,761,480 Methods of forming field effect transistor (FET) and non-FET circuit elements on a semiconductor-on-insulator...
One illustrative method disclosed includes forming an isolation structure so as to define first and second active regions on the SOI substrate, forming a field...
US-9,761,479 Manufacturing method for semiconductor substrate
A technique disclosed herein relates to a manufacturing method for a semiconductor substrate having the bonded interface with high bonding strength without...
US-9,761,478 Substrate transport apparatus
A substrate transport apparatus including a frame, an upper arm rotatably mounted to the frame about a shoulder axis, a forearm rotatably mounted to the upper...
US-9,761,477 Pre-package and methods of manufacturing semiconductor package and electronic device using the same
Methods of fabricating semiconductor packages are provided. One of the methods includes forming a protection layer including metal on a first surface of a...
US-9,761,476 Dicing film and dicing die-bonding film
The present invention relates to a dicing film including: a substrate film; and a cohesive layer, wherein a storage modulus of the cohesive layer at 30.degree....
US-9,761,475 Film for semiconductor device production, method for producing film for semiconductor device production, and...
The present invention relates to a film for semiconductor device production, which includes: a separator; and a plurality of adhesive layer-attached dicing...
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