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Patent # Description
US-9,768,340 Photodiode with a dark current suppression junction
This invention relates to field photodiodes based on PN junctions that suffer from dark current leakage. An NBL is added to prove a second PN junction with the...
US-9,768,339 Optoelectronic detectors having a dilute nitride layer on a substrate with a lattice parameter nearly matching GaAs
Optoelectronic detectors having one or more dilute nitride layers on substrates with lattice parameters matching or nearly matching GaAs are described herein. A...
US-9,768,338 Multi-source optimal reconfigurable energy harvester
Provided is an energy harvesting device, including a solar cell including at least one active layer for receiving a first range of electromagnetic frequencies,...
US-9,768,337 Photonic bandgap structure
A photonic bandgap structure having multiple stacked layers has a thickness from the top of its top layer to the bottom of its bottom layer of less than one...
US-9,768,336 Solar cell module
A solar cell module includes a plurality of solar cells and includes first and second solar cells positioned adjacent to each other in a first direction, the...
US-9,768,334 High efficiency solar cells with quantum dots for IR pumping
A photovoltaic (PV) device including: (a) a p-n junction having (i) p-type silicon substrate with an Al-doped P++ surface, (ii) a wide band intrinsic AlP region...
US-9,768,333 Microbially-mediated method for synthesis of non-oxide semiconductor nanoparticles
The invention is directed to a method for producing non-oxide semiconductor nanoparticles, the method comprising: (a) subjecting a combination of reaction...
US-9,768,332 Infrared detection element
This infrared detection element includes a buffer layer (InAsSb layer) 3, a buffer layer (InAs layer) 4, and a light absorption layer (InAsSb layer) 5. A...
US-9,768,331 Screen printing electrical contacts to nanowire areas
A process is provided for contacting a nanostructured surface. The process may include (a) providing a substrate having a nanostructured material on a surface,...
US-9,768,330 Method and optoelectronic structure providing polysilicon photonic devices with different optical properties in...
Method and structural embodiments are described which provide an integrated structure using polysilicon material having different optical properties in...
US-9,768,329 Multi-junction optoelectronic device
An optoelectronic semiconductor device is disclosed. The optoelectronic device comprises a plurality of stacked p-n junctions. The optoelectronic semiconductor...
US-9,768,328 Transparent film, transparent electro-conductive laminate, and touch panel, solar cell, and display device...
A transparent electro-conductive laminate comprising: a substrate film made of a polyimide; and a thin film made of an electro-conductive material and stacked...
US-9,768,327 Etching techniques for semiconductor devices
Fabricating a semiconductor device can include forming a metal seed region over a substrate. The method can include forming a mask over a first portion of the...
US-9,768,326 Fabrication of solar cells with electrically conductive polyimide adhesive
The present disclosure provides a method of manufacturing a solar cell comprising: providing a semiconductor growth substrate; depositing on said growth...
US-9,768,325 Diodes and fabrication methods thereof
Diodes and fabrication methods thereof are presented. The diodes include, for instance: a first semiconductor region disposed at least partially within a...
US-9,768,324 Co-planar oxide semiconductor TFT substrate structure and manufacture method thereof
Provided is a co-planar oxide semiconductor TFT substrate structure, in which an active layer includes a main body and a plurality of short channels connected...
US-9,768,323 Manufacture method of dual gate oxide semiconductor TFT substrate and structure thereof
A dual gate oxide semiconductor TFT substrate is made by utilizing a halftone mask to implement one photo process, which accomplishes patterning of an oxide...
US-9,768,322 Metal oxide TFT with improved source/drain contacts and reliability
A method including providing a substrate with a gate, a layer of gate insulator material adjacent the gate, and a layer of metal oxide semiconductor material...
US-9,768,320 Semiconductor device
Disclosed is a semiconductor device including two oxide semiconductor layers, where one of the oxide semiconductor layers has an n-doped region while the other...
US-9,768,319 Modulation circuit and semiconductor device including the same
A modulation circuit includes a load and a transistor serving as a switch. The transistor has an oxide semiconductor layer in which hydrogen concentration is...
US-9,768,318 Semiconductor device and method for manufacturing the same
A miniaturized transistor, a transistor with low parasitic capacitance, a transistor with high frequency characteristics, or a semiconductor device including...
US-9,768,317 Semiconductor device, manufacturing method of semiconductor device, and electronic device
Provided is a semiconductor device which can suppress an increase in oxygen vacancies in an oxide semiconductor layer and a manufacturing method of the...
US-9,768,316 Oxide semiconductor thin film and thin film transistor
Provided is a crystalline oxide semiconductor thin film comprising only bixbyite-structured In.sub.2O.sub.3 phase, suitable as a channel layer material for a...
US-9,768,315 Semiconductor device and display device having the same
A change in electrical characteristics can be inhibited and reliability can be improved in a semiconductor device using a transistor including an oxide...
US-9,768,314 Method for manufacturing semiconductor device
To reduce defects in an oxide semiconductor film in a semiconductor device. To improve electrical characteristics of and reliability in the semiconductor device...
US-9,768,313 Devices having transition metal dichalcogenide layers with different thicknesses and methods of manufacture
An embodiment is a structure including a first active device in a first region of a substrate, the first active device including a first layer of a...
US-9,768,312 Thin film transistor, manufacturing method thereof, array substrate, and display device
Embodiments of the present invention disclose a manufacturing method of a thin film transistor, a thin film transistor, an array substrate and a display device....
US-9,768,311 Semiconductor tunneling device
The present invention concerns a semiconductor tunneling Field-Effect device including a source, a drain, at least one elongated semiconductor structure...
US-9,768,310 Thin film transistor, organic light-emitting diode display including the same, and manufacturing method thereof
A TFT, OLED display including the same, and manufacturing method thereof are disclosed. In one aspect, the TFT includes a first gate electrode formed over a...
US-9,768,309 Thin film transistor and thin film transistor array panel including the same
A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode...
US-9,768,308 Low temperature poly-silicon thin film transistor and fabrication method thereof, array substrate and display...
A low temperature poly-silicon thin film transistor and a fabrication method thereof, an array substrate and a display device are provided. The method...
US-9,768,307 Semiconductor device and method for manufacturing the same
An object is to provide a structure of a transistor which has a channel formation region formed using an oxide semiconductor and a positive threshold voltage...
US-9,768,306 Array substrate and display device
An array substrate and a display device are provided. A gate insulating layer and a gate electrode are formed on a semiconductor layer in sequence, the gate...
US-9,768,305 Gradient ternary or quaternary multiple-gate transistor
An integrated circuit structure includes a semiconductor substrate; insulation regions over the semiconductor substrate; and an epitaxy region over the...
US-9,768,304 Method of fabricating a FINFET having a gate structure disposed at least partially at a bend region of the...
A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed...
US-9,768,303 Method and structure for FinFET device
A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and...
US-9,768,302 Semiconductor structure and fabricating method thereof
A semiconductor structure and a method of fabricating the semiconductor structure are disclosed herein. The semiconductor structure includes a substrate, a...
US-9,768,301 Short channel effect suppression
A semiconductor device includes a semiconductor substrate having a first region and a second region. The first region includes a first set of fin structures,...
US-9,768,300 Semiconductor devices including a stressor in a recess and methods of forming the same
Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench...
US-9,768,299 Method to form strained channel in thin box SOI structures by elastic strain relaxation of the substrate
Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate...
US-9,768,298 Memory cell array and cell structure thereof
A memory device includes a substrate and a memory array. The substrate has a continuous active region. The memory array is disposed in the continuous active...
US-9,768,297 Process design to improve transistor variations and performance
The present disclosure relates to a transistor device having an epitaxial carbon layer and/or a carbon implantation region that provides for a low variation of...
US-9,768,296 I-shaped gate electrode for improved sub-threshold MOSFET performance
Metal-oxide-semiconductor (MOS) transistors with reduced subthreshold conduction, and methods of fabricating the same. Transistor gate structures are fabricated...
US-9,768,295 Semiconductor devices having super-junction trenches with conductive regions and method of making the same
In one embodiment, the semiconductor devices relate to using one or more super-junction trenches for termination.
US-9,768,294 Method for producing semiconductor device and semiconductor device
A semiconductor device includes a fin-shaped semiconductor layer, a first insulating film formed around the fin-shaped semiconductor layer, a first metal film...
US-9,768,293 Laterally diffused metal-oxide-semiconductor (LDMOS) transistor with a vertical channel region
A laterally diffused metal-oxide-semiconductor (LDMOS) transistor with a vertical channel region is provided. A first semiconductor region is formed over a...
US-9,768,292 Laterally diffused metal oxide semiconductor device and manufacturing method therefor
Provided is a manufacturing method for a laterally diffused metal oxide semiconductor device, comprising the following steps: growing an oxide layer on a...
US-9,768,291 Semiconductor device having a non-depletable doping region
A semiconductor device includes a plurality of compensation regions of a vertical electrical element arrangement, a plurality of drift regions of the vertical...
US-9,768,290 Semiconductor device with metal-filled groove in polysilicon gate electrode
A semiconductor device includes a semiconductor substrate, a body region of a first conductivity type in the substrate, a source region of a second conductivity...
US-9,768,289 Field effect transistor with conduction band electron channel and uni-terminal response
A uni-terminal transistor device is described. In one embodiment, an n-channel transistor having p-terminal characteristics comprises a first semiconductor...
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