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Patent # Description
US-9,768,288 Carbon nanostructure device fabrication utilizing protect layers
Hall effect devices and field effect transistors are formed incorporating a carbon-based nanostructure layer such as carbon nanotubes and/or graphene with a...
US-9,768,287 Switching device
A switching device includes a semiconductor substrate having a first element range including first trenches for gates, and an ineffective range not including...
US-9,768,286 Semiconductor device
In a back surface hole injection type diode, by more effectively securing the effect of hole injection from the back surface of a semiconductor substrate, the...
US-9,768,285 Semiconductor device and method of manufacture
In one embodiment, an IGBT is formed to include a region of semiconductor material. Insulated gate structures are disposed in region of semiconductor material...
US-9,768,284 Bipolar semiconductor device having a charge-balanced inter-trench structure
There are disclosed herein various implementations of a bipolar semiconductor device having a charge-balanced inter-trench structure. Such a device includes a...
US-9,768,283 High-voltage semiconductor structure
A high-voltage semiconductor structure including a substrate, a first doped region, a well, a second doped region, a third doped region, a fourth doped region,...
US-9,768,282 Bipolar transistor having collector with grading
This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having at least one grading in the collector. One aspect of this...
US-9,768,281 Method for manufacturing semiconductor device
An object is to provide a semiconductor device including a semiconductor element which has favorable characteristics. A manufacturing method of the present...
US-9,768,279 Semiconductor device and manufacturing method thereof
To provide a transistor formed using an oxide semiconductor film with reduced oxygen vacancies. To provide a semiconductor device that operates at high speed....
US-9,768,278 Reduction of Fin loss in the formation of FinFETS
A method includes forming a dummy gate stack on a top surface and a sidewall of a middle portion of a semiconductor fin, and forming a spacer layer. The spacer...
US-9,768,277 Method and apparatus of forming an integrated circuit with a strained channel region
Various methods include providing a substrate, forming a projection extending upwardly from the substrate, the projection having a channel region therein, and...
US-9,768,276 Method and structure of forming FinFET electrical fuse structure
An e-Fuse structure is provided on a surface of an insulator layer of a semiconductor-on-insulator substrate (SOI). The e-Fuse structure includes a first metal...
US-9,768,275 Array substrate for fringe field switching mode liquid crystal display device and method of fabricating the same
An array substrate for a liquid crystal display (LCD) device includes a common line and gate lines. The array substrate includes a first, second, and third...
US-9,768,274 Laterally-graded doping of materials
A method includes defining, on a surface of a material, a plurality of discrete portions of a surface as surface elements having at least one of a...
US-9,768,273 Method of forming a trench using epitaxial lateral overgrowth
In one aspect, a method of forming a trench in a semiconductor material includes forming a first dielectric layer on a semiconductor substrate. The first...
US-9,768,272 Replacement gate FinFET process using a sit process to define source/drain regions, gate spacers and a gate cavity
A replacement gate FinFET manufacturing process in which the source/drain regions, gate structure and gate spacer are all defined by utilizing a single sidewall...
US-9,768,271 Methods, devices, and systems related to forming semiconductor power devices with a handle substrate
Methods of manufacturing device assemblies, as well as associated semiconductor assemblies, devices, systems are disclosed herein. In one embodiment, a method...
US-9,768,270 Method of selectively depositing floating gate material in a memory device
Undesirable metal contamination from a selective metal deposition process can be minimized or eliminated by employing a first material layer on a bevel and a...
US-9,768,269 Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same
An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth...
US-9,768,268 Semiconductor device
A semiconductor device according to an embodiment switches high-frequency signals and includes a semiconductor layer of a first conductivity type. A first layer...
US-9,768,267 Surrounding gate semiconductor device
An SGT is produced by forming a first insulating film around a fin-shaped semiconductor layer, forming a pillar-shaped semiconductor layer in an upper portion...
US-9,768,266 Three-dimensional semiconductor memory devices and methods of fabricating the same
Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure...
US-9,768,265 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a semiconductor layer, a first electrode, first and second oxide layers, and a storage...
US-9,768,263 Semiconductor devices and FinFET devices
A fin field effect transistor (FinFET) device includes a substrate and a template material over the substrate. The template material absorbs lattice mismatches...
US-9,768,262 Embedded carbon-doped germanium as stressor for germanium nFET devices
Carbon-doped germanium stressor regions are formed in an nFET device region of a germanium substrate and at a footprint of a functional gate structure. The...
US-9,768,261 Semiconductor structure and method of forming the same
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure protruding from the...
US-9,768,260 Fabrication method of silicon carbide semiconductor apparatus and silicon carbide semiconductor apparatus...
Process (A) of preparing a silicon carbide substrate of a first conductivity type; process (B) of forming an epitaxial layer of the first conductivity type on...
US-9,768,259 Controlled ion implantation into silicon carbide using channeling and devices fabricated using controlled ion...
Methods of forming a semiconductor structure include the use of channeled implants into silicon carbide crystals. Some methods include providing a silicon...
US-9,768,258 Substrate structure, semiconductor component and method
In an embodiment, a substrate structure includes a support substrate, a buffer structure arranged on the support substrate, the buffer structure including an...
US-9,768,257 Semiconductor device
A high electron mobility transistor having a channel layer, electron supply layer, source electrode, and drain electrode is included so as to have a cap layer...
US-9,768,256 Formation of dislocations in source and drain regions of FinFET devices
Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and...
US-9,768,255 Semiconductor devices including contact structures that partially overlap silicide layers
Semiconductor devices are provided. A semiconductor device includes a substrate. The semiconductor device includes an isolation layer defining active portions...
US-9,768,254 Leakage-free implantation-free ETSOI transistors
A semiconductor device includes an extremely thin semiconductor-on-insulator substrate (ETSOI) having a base substrate, a thin semiconductor layer and a buried...
US-9,768,253 Semiconductor device including crystal defect region and method for manufacturing the same
A semiconductor device includes: an n type semiconductor layer including an active region and an inactive region; an element structure formed in the active...
US-9,768,252 Vertical gate-all-around field effect transistors
Semiconductor devices and methods of forming the same are provided. A template layer is formed on a substrate, the template layer having a recess therein. A...
US-9,768,251 Method for manufacturing a semiconductor structure, semiconductor structure, and electronic device
A method for manufacturing a semiconductor structure comprises the steps of: providing a substrate including a first semiconductor material; forming a...
US-9,768,250 Semiconductor devices including gate contacts
A semiconductor device includes a substrate. The semiconductor device includes a gate electrode on the substrate. The semiconductor device includes a gate...
US-9,768,249 Trigate transistor structure with unrecessed field insulator and thinner electrodes over the field insulator
Techniques related to integrated circuits having MOSFETs with an unrecessed field insulator and thinner electrodes over the field insulator of ICs, systems...
US-9,768,248 Semiconductor device having diode characteristic
According to one embodiment, a semiconductor device is provided. The semiconductor device has a first region formed of semiconductor and a second region formed...
US-9,768,247 Semiconductor device having improved superjunction trench structure and method of manufacture
A semiconductor device includes a charge-compensating region with a first structure disposed adjoining an end portion of the charge-compensating region. The...
US-9,768,246 Semiconductor device and method for producing semiconductor device
Hydrogen atoms and crystal defects are introduced into an n- semiconductor substrate by proton implantation. The crystal defects are generated in the n-...
US-9,768,245 High breakdown voltage microelectronic device isolation structure with improved reliability
A microelectronic device contains a high voltage component having a high voltage node and a low voltage node. The high voltage node is isolated from the low...
US-9,768,244 Semiconductor device
A semiconductor device includes a first electrode layer and a second electrode layer. The first electrode layer extends in a first direction. The second...
US-9,768,243 Structure of resistor
A plurality of openings is formed in a dielectric layer formed on a semiconductor substrate. The plurality of openings comprises a first opening extending to...
US-9,768,242 Organic light emitting diode display
An organic light emitting diode display includes: a plurality of pixels including a first pixel, a second pixel, and a third pixel connected to the plurality of...
US-9,768,241 Thin film transistor array substrate and organic light-emitting diode display
A thin film transistor (TFT) array substrate includes: a substrate; a first insulation layer on the substrate; a capacitor including a lower electrode on the...
US-9,768,240 Thin film transistor array substrate and organic light-emitting diode display including the same
A thin film transistor (TFT) array substrate and organic light-emitting diode (OLED) display including the same are disclosed. In one aspect, the array...
US-9,768,239 Light-emitting device and display device
Although an organic resin substrate is highly effective at reducing the weight and improving the shock resistance of a display device, it is required to improve...
US-9,768,238 Electrical device to mask systematic luminance variation
An electrical device containing pixel circuits, where at least one resistor is present within one pixel circuit to mask systematic luminance variation in...
US-9,768,237 Organic light emitting diode display panel and organic light emitting diode display device containing the same
An organic light emitting diode display panel is disclosed, which comprises: a first substrate with an organic light emitting layer formed thereon; a second...
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