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Patent # Description
US-9,767,930 Suspended upper internals for compact nuclear reactor including a mid-hanger plate
A pressure vessel comprises an upper vessel section and a lower vessel section. A nuclear reactor core comprising fissile material is disposed the lower vessel...
US-9,767,929 Advanced grid spacer design for a nuclear fuel assembly
A new, improved grid spacer for a nuclear fuel assembly is provided, comprising several straps which intersect each other alternatively to form a plurality of...
US-9,767,928 Nuclear reactor fuel assembly
A nuclear reactor fuel assembly includes a plurality of fuel rods, a plurality of guide channels, two nozzles, one of which has a bearing plate with openings,...
US-9,767,927 Particulate removal system
A particulate removal apparatus and method are used to capture and remove particulates from nuclear reactor core coolant during normal operation. Bottom nozzle,...
US-9,767,926 Modular nuclear fission waste conversion reactor
A modular, nuclear waste conversion reactor that continuously produces usable energy while converting U-238 and/or other fertile waste materials to fissionable...
US-9,767,925 Method, apparatus, and system to reduce neutron production in small clean fusion reactors
The invention is for a system and method to reduce neutron production from a deuterium-helium-3 (D-.sup.3He) fueled, steady-state, small nuclear fusion reactor....
US-9,767,924 Fast memory array repair using local correlated electron switch (CES) memory cells
An integrated circuit is provided for self-repair of a memory array. The circuit includes first word lines coupled to first memory rows of the memory array, one...
US-9,767,923 Three-dimensional flash memory system
A three-dimensional flash memory system is disclosed.
US-9,767,922 Memory device and memory system having repair unit modification function
Provided is a memory device including a memory cell array including a normal area in which a plurality of memory cells are arranged, and a redundancy area in...
US-9,767,921 Timing based arbiter systems and circuits for ZQ calibration
Systems and apparatuses are provided for an arbiter circuit for timing based ZQ calibration. An example system includes a resistor and a plurality of chips....
US-9,767,920 Semiconductor memory devices and memory systems including the same
A semiconductor memory device includes a memory cell array, an input/output (I/O) gating circuit, an error decision circuit and an error check and correction...
US-9,767,919 Systems and methods for testing a semiconductor memory device having a reference memory array
Semiconductor memory testing devices and methods are disclosed. In one respect, a device is disclosed that includes a first memory cell array having a first...
US-9,767,918 System including hierarchical memory modules having different types of integrated circuit memory devices
Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a...
US-9,767,917 Mitigation scheme for SRAM functionality
An system and method are configured to degrade a memory cell PFET voltage based on a sensor reading of a current operating point. This will enable additional...
US-9,767,916 Shift register and display apparatus
The present disclosure relates to a shift register and a display apparatus, wherein the shift register comprising an input module, a pull-down module, an...
US-9,767,915 One-time programmable device with integrated heat sink
Junction diodes fabricated in standard CMOS logic processes can be used as program selectors with at least one heat sink or heater to assist programming for...
US-9,767,914 Durable maintenance of memory cell electric current sense window following program-erase operations to a...
A method of a state machine executing instructions related to program-erase operations performed on a non-volatile memory is disclosed. The method includes...
US-9,767,913 Memory system performing read of nonvolatile semiconductor memory device
According to one embodiment, a memory system includes a nonvolatile semiconductor memory device, a voltage generation unit and a control unit. The nonvolatile...
US-9,767,912 Nonvolatile memory system that erases memory cells when changing their mode of operation
An method of operating a memory system including a plurality of memory cells includes changing an operation mode at least some of the memory cells which operate...
US-9,767,911 Dynamic programming of advanced nanometer flash memory
An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed.
US-9,767,910 Semiconductor memory device and memory system
A semiconductor memory device includes: a first memory unit including first to fourth memory cells; a second memory unit including fifth to eighth memory cells;...
US-9,767,909 Memory cell programming utilizing conditional enabling of memory cells
Methods of operating a memory include determining indications of programming voltages sufficient to program respective groups of memory cells of a plurality of...
US-9,767,908 Semiconductor memory device that applies an initial pass voltage followed by a final pass voltage to...
A non-volatile semiconductor memory device includes a first memory cell above a substrate and electrically connected to a first word line, a second memory cell...
US-9,767,907 Row decoder for a non-volatile memory device, having reduced area occupation
A row decoder for a non-volatile memory device includes an input and pre-decoding module that receives address signals and generates pre-decoded address...
US-9,767,906 Semiconductor memory device including three-dimensional array structure and memory system including the same
A semiconductor memory device may include first and second sub-cell strings. The first sub-cell string may be coupled to a common source line at an end of the...
US-9,767,905 Scan chain circuits in non-volatile memory
A bit scan circuit includes N scan blocks corresponding with an N-bit string of binary data. The string is scanned using an input clock signal to count the...
US-9,767,904 Memory with three transistor memory cell device
Memory, memory devices, and a method for a backup sequence are disclosed. In one such memory device, sense circuitry and page buffers are coupled between a...
US-9,767,903 Nonvolatile memory module having dual-port DRAM
A memory module includes a nonvolatile memory device and a volatile memory device connected to a first data channel through a first input/output port and to a...
US-9,767,902 Non-volatile composite nanoscopic fabric NAND memory arrays and methods of making same
A non-volatile nanotube switch and memory arrays constructed from these switches are disclosed. A non-volatile nanotube switch includes a conductive terminal...
US-9,767,901 Circuits having selector devices with different I-V responses
An integrated circuit is provided. In an example, the integrated circuit includes a first address line, a selector device electrically coupled to the first...
US-9,767,900 Method, apparatus and device for operating logical operation array of resistive random access memory
A logical operation array of a resistive random access memory includes at least one logical operation unit; each logical operation unit includes multiple...
US-9,767,899 Access signal conditioning for memory cells in an array
A memory is described having an array including two-terminal resistive memory elements (MEs) to retain stored data in an absence of electrical power and a...
US-9,767,898 Memory device with reduced neighbor memory cell disturbance
In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes a memory cell, digit line driver, access line driver, clamping...
US-9,767,897 Conductive metal oxide structures in non-volatile re-writable memory devices
A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a...
US-9,767,896 Apparatuses and methods for accessing memory cells in semiconductor memories
Apparatuses and methods for accessing a memory cell are described. An example apparatus includes a first voltage circuit coupled to a node and is configured to...
US-9,767,895 Semiconductor memory device and controlling method thereof
The control unit performs a first writing operation to obtain a first threshold voltage distribution, and a second writing operation to obtain a second...
US-9,767,894 Programming memories with stepped programming pulses
Memories and methods for programming memories with multi-step programming pulses are provided. One method includes applying a plurality of programming pulses to...
US-9,767,893 Semiconductor memory device that can stably perform writing and reading without increasing current consumption...
Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage...
US-9,767,892 Memory elements with dynamic pull-up weakening write assist circuitry
Integrated circuits with an array of memory cells are provided. Each memory cell may include at least one pair of cross-coupled inverters, write access...
US-9,767,891 Passive SRAM write assist
Passive write assist passively improves SRAM performance (e.g., write margin speed) while reducing manufacturing costs (e.g., die area, packaging) and operating...
US-9,767,890 Operation aware auto-feedback SRAM
A static random-access memory is described. The SRAM includes a storage cell and a voltage supply to supply the storage cell with a reduced voltage during a...
US-9,767,889 Programmable pad capacitance for supporting bidirectional signaling from unterminated endpoints
A die is provided having an unterminated endpoint that capacitively loads its input impedance with a capacitance from capacitor while acting as a receiving...
US-9,767,888 Methods and devices for high-sensitivity memory interface receiver
Embodiments relate to systems, methods and computer-readable media to enable design and creation of receiver circuitry. One embodiment is a receiver apparatus...
US-9,767,887 Memory device, memory module including the same, and memory system including the same
A memory device includes a first memory cell, a second memory cell, a precharge circuit, a sense amplifier, a switch circuit, and a controller. The first memory...
US-9,767,886 Memory command received within two clock cycles
A technique to increase transfer rate of command and address signals via a given number of command and address pins in each of one or more integrated circuit...
US-9,767,885 Semiconductor systems for fast sensing speed and correct amplification
A semiconductor device may include a power control signal generator and a sense amplifier circuit. The power control signal generator may generate a first power...
US-9,767,884 Memory with termination circuit
A semiconductor integrated circuit is described. A transmitter-receiver transmits and receives data to and from outside by a first external terminal and...
US-9,767,883 Semiconductor memory device that performs a refresh operation
A semiconductor memory device includes a memory circuit including a plurality of memory cells and a refresh control circuit. The refresh control circuit is...
US-9,767,882 Method of refreshing memory device
A method of refreshing a memory device includes performing normal refresh operations on memory cell rows in response to a refresh command and performing...
US-9,767,881 Dynamic random access memory with fully independent partial array refresh function
A dynamic random access memory device includes a plurality of memory subblocks. Each subblock has a plurality of wordlines whereto a plurality of data store...
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