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Patent # Description
US-9,767,067 Baseboard management systems and methods with distributed intelligence for multi-node platforms
Baseboard management systems and methods with distributed intelligence for multi-node platforms. In an illustrative, non-limiting embodiment, an Information...
US-9,767,066 Wireless protocol communication bridge and system comprising bridge
A bridge for linking a first and a second wireless communication device and translating between differing wireless protocols is described and taught. The bridge...
US-9,767,065 Dynamic vehicle bus subscription
A method of controlling access at a vehicle to information communicated over a vehicle bus includes: storing one or more electronic control unit (ECU)...
US-9,767,064 Low power universal serial bus
Systems and method for operating a low power universal serial bus are described herein. A universal serial bus port includes a link layer and protocol layer...
US-9,767,063 Adaptive access control for hardware blocks
System and method for providing adaptive access to a hardware block on a computer system. In one embodiment, a method includes receiving a first access request...
US-9,767,062 Low power parallelization to multiple output bus widths
A Serializer/Deserializer (SerDes) is described with an architecture that simultaneously provides flexibility for many different gear ratios as well as reduced...
US-9,767,061 Electronic device
An electronic device includes: a communication module; an input module; a display; an interface; at least one sensor; a memory; and a processor module. The...
US-9,767,060 USB type C to MHL M1 dead battery charging
Methods and apparatus, including computer program products, are provided for cable, connectors, and/or other devices. In one aspect there is provided an...
US-9,767,059 Multimedia USB device server
The present invention relates to a multimedia server means, comprising a plurality of universal serial bus, USB, connections and a processing means configured...
US-9,767,058 Method and apparatus for scalable low latency solid state drive interface
A solid state drive (SSD) apparatus including a plurality of solid state drives, a channel-interleaved interface operably coupled to the solid state drives, and...
US-9,767,057 Hardware data structure for tracking partially ordered and reordered transactions
Methods and hardware data structures are provided for tracking ordered transactions in a multi-transactional hardware design comprising one or more slaves...
US-9,767,056 Method for controlling transaction exchanges between two integrated circuits
Transaction exchanges are controlled between two integrated circuits in a system having the integrated circuits (ICs), a power supply supplying power to a link...
US-9,767,055 Sensor transmission device and method for transmitting payload data from multiple sensors to a bus control...
A method is described for assigning payload data from a bus data packet to different sensor transmission devices, a bus control device being connected to a data...
US-9,767,054 Data transfer control device and memory-containing device
An image processing module input/output port in a DMAC includes an input part which receives second address information and an addressing request signal from an...
US-9,767,053 Memory controller and memory system including the same
A memory controller connected with a storage medium via a plurality of channels is provided which includes a signal processing block including a plurality of...
US-9,767,052 Information processing apparatus, information processing method, and storage medium
An information processing apparatus includes a first memory, and a processor coupled to the first memory and configured to: specify a number of virtual machines...
US-9,767,051 Scalable, parameterizable, and script-generatable buffer manager architecture
A buffer manager is generated by executing a script with respect to a buffer architecture template and a configuration file specifying parameters for the buffer...
US-9,767,050 Memory systems that adjust an auto-refresh operation responsive to a self-refresh operation history
A memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a plurality of dynamic memory cells....
US-9,767,049 Isolated KVM combiner for multi-network computer system having a video processor
The present invention presents apparatuses and systems for operating multiple computers from a single keyboard and a single mouse and view composite videos...
US-9,767,048 Initializing I/O devices
A data processing system is provided which includes a processor nest communicatively coupled to an input/output bus by a bus controller, and a service interface...
US-9,767,047 Methods and systems for filtering communication between peripheral devices and mobile computing devices
The embodiments are directed to methods and systems for sending and receiving signals between one or more peripheral devices connected to a dongle system and an...
US-9,767,046 Modular device, system, and method for reconfigurable data distribution
Systems, apparatus, and methods for a reconfigurable integrated system integrated onto a single circuit board are described herein. An embodiment includes a CPU...
US-9,767,045 Control for authenticated accesses to a memory device
The embodiments of the invention describe settings, commands, command signals, flags, attributes, parameters or the like for signed access prior to allowing...
US-9,767,044 Secure memory repartitioning
Secure memory repartitioning technologies are described. A processor includes a processor core and a memory controller coupled between the processor core and...
US-9,767,043 Enhancing lifetime of non-volatile cache by reducing intra-block write variation
A method, a system and a computer-readable medium for writing to a cache memory are provided. The method comprises maintaining a write count associated with a...
US-9,767,042 Enhancing cache performance by utilizing scrubbed state indicators associated with cache entries
Systems and methods for improving write-back cache performance by utilizing scrubbed state indicators associated with the cache entries. The example system may...
US-9,767,041 Managing sectored cache
Apparatus, systems, and methods to manage memory operations are described. In one example, a controller comprises logic to receive a first transaction to...
US-9,767,040 System and method for generating and storing real-time analytics metric data using an in memory buffer service...
In an example, a processing system of a database system may categorize event data taken from logged interactions of users with a multi-tenant information system...
US-9,767,039 Increasing granularity of dirty bit information in hardware assisted memory management systems
In a computer system having virtual machines, one or more unused bits of a guest physical address range are allocated for aliasing so that multiple virtually...
US-9,767,038 Systems and methods for accessing a unified translation lookaside buffer
Systems and methods for accessing a unified translation lookaside buffer (TLB) are disclosed. A method includes receiving an indicator of a level one...
US-9,767,037 Technologies for position-independent persistent memory pointers
Technologies for persistent memory pointer access include a computing device having a persistent memory including one or more nonvolatile regions. The computing...
US-9,767,036 Page state directory for managing unified virtual memory
A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory...
US-9,767,035 Pass-through tape access in a disk storage environment
A command to write data to a virtual location is received at a disk storage system. The virtual location is mapped to a tape storage system. A record is...
US-9,767,034 Operating a FIFO memory
The present invention concerns a method of operating a first-in first-out memory (9) arranged to store measurement data samples measured by a plurality of data...
US-9,767,033 Method and apparatus for managing cache memory in communication system
In the present invention, a base station determines from a communication system whether a first content, which is requested by a mobile terminal, is saved on a...
US-9,767,032 Systems and methods for cache endurance
A cache and/or storage module may be configured to reduce write amplification in a cache storage. Cache layer write amplification (CLWA) may occur due to an...
US-9,767,031 Dynamic structural management of a distributed caching infrastructure
Embodiments of the present invention provide a method, system and computer program product for the dynamic structural management of an n-Tier distributed...
US-9,767,030 Sizing a write cache buffer based on emergency data save parameters
Embodiments relate to saving data upon loss of power. An aspect includes sizing a write cache buffer based on parameters related to carrying out this emergency...
US-9,767,029 Data decompression using a construction area
For serving sequential read patterns from a compressed journal storage system, a construction area cache algorithm is used to temporarily store the read and...
US-9,767,028 In-memory interconnect protocol configuration registers
Systems, apparatuses, and methods for moving the interconnect protocol configuration registers into the main memory space of a node. The region of memory used...
US-9,767,027 Private memory regions and coherency optimization by controlling snoop traffic volume in multi-level cache...
A system for optimizing cache coherence message traffic volume is disclosed. The system includes a plurality of caches in a multi-level memory hierarchy and a...
US-9,767,026 Providing snoop filtering associated with a data buffer
In one embodiment, a conflict detection logic is configured to receive a plurality of memory requests from an arbiter of a coherent fabric of a system on a chip...
US-9,767,025 Write-only dataless state for maintaining cache coherency
Systems and methods for maintaining cache coherency in a multiprocessor system with shared memory, including a write-data-invalid (WDI) state configured to...
US-9,767,024 Cache closure and persistent snapshot in dynamic code generating system software
Systems and methods may provide translation cache closure and consistent data recovery in dynamic code generating system. An apparatus may group translation...
US-9,767,023 Method of controlling data writing to persistent storage device
A second computer transmits, to a first computer, confirmation data including identification information and a version number of copy data updated in a cache....
US-9,767,022 In-memory buffer service
A capture service running on an application server receives events from a client application running on an application server to be stored in a data store and...
US-9,767,021 Optimizing destaging of data to physical storage devices
Described are techniques for destaging data. Write data for write operations are stored in cache page(s). The cache may be partitioned into cache pages and...
US-9,767,020 Systems and methods for faster read after write forwarding using a virtual address
Methods for read after write forwarding using a virtual address are disclosed. A method includes determining when a virtual address has been remapped from...
US-9,767,019 Pauseless garbage collector write barrier
An example method of managing memory includes identifying a first object of the first type to update, the first object being stored on a heap. The method also...
US-9,767,018 Allocation aware heap fragmentation metrics
An illustrative embodiment of a computer-implemented method for estimating heap fragmentation in real time, models a runtime view of free heap memory, models a...
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