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| Patent # | Description |
|---|---|
| US-9,779,058 |
Modulating processsor core operations Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for reducing processor latency through the use of dedicated... |
| US-9,779,057 |
Autonomous memory architecture An autonomous memory device in a distributed memory sub-system can receive a database downloaded from a host controller. The autonomous memory device can pass... |
| US-9,779,056 |
Communication server, communication system, program, and communication
method A communication server includes a terminal management unit managing data identifying each of a plurality of communication terminals in association with group... |
| US-9,779,055 |
Integrated circuit device and signal processing method in integrated
circuit device An integrated circuit device has a first processing unit, a second processing unit, an external interface, and a control program controlling the first... |
| US-9,779,054 |
System, apparatus and method for centralized management of security
inspection devices via field bus network Disclosed is system, apparatus and method for centralized management of security inspection devices, which provide connection and communication between local... |
| US-9,779,053 |
Physical interface for a serial interconnect An apparatus that includes a physical interface for a serial interconnect is provided. The physical interface includes a buffer that is selectable to function... |
| US-9,779,052 |
PCIe bridge transformation device and method thereof A PCIe bridge transformation device and a method thereof are provided, which is adapted to a storage unit in a lock state. The transformation device includes a... |
| US-9,779,051 |
Computer system and a computer device A computer system is provided. The computer system includes a hub board, a common bus, and a plurality of Sibling boards. The hub board has an I/O controller... |
| US-9,779,050 |
Allocating virtual resources to root PCI bus Systems and methods for allocating virtual resources to a root PCI bus. An example method may comprise: intercepting, by a hypervisor being executed by a... |
| US-9,779,049 |
Data transfer system and method of controlling the same A data transfer system is disclosed, which comprises a serial controller and a switch device. The switch device includes a first serial port, a second serial... |
| US-9,779,048 |
USB type-C cable and method for reading/writing a chip in a USB type-C
cable A method for reading/writing a chip in a USB type-C cable comprises converting a read/write command into unstructured vendor defined message (UVDM) that is... |
| US-9,779,047 |
Universal intelligent platform management interface (IPMI) host to
baseboard management controller (BMC)... Aspects of the disclosure relate to systems and methods for performing a universal Intelligent Platform Management Interface (IPMI) host-to-baseboard management... |
| US-9,779,046 |
Electronic apparatus and port control method for locking downstream USB
ports A method of an embodiment enables locking of downstream ports of a USB hub controller in an electronic apparatus. The method includes the determination step,... |
| US-9,779,045 |
Electronic controller to be connected to program tool A first external tool (10A) serially connected to an electronic controller (20A) through a pair of communication lines (LANH, LANN) applies a high voltage (Vaa)... |
| US-9,779,044 |
Access extent monitoring for data transfer reduction A data processor system includes a local memory, a processor core, and an extent monitor. The local memory stores a block of data at a task memory location that... |
| US-9,779,043 |
Techniques for handling queued interrupts in a data processing system A technique for handling queued interrupts includes accumulating respective backlog counts for respective event paths. The background counts track a number of... |
| US-9,779,042 |
Resource management in a multicore architecture A resource management and task allocation controller for installation in a multicore processor having a plurality of interconnected processor elements providing... |
| US-9,779,041 |
Enabling poll/select style interfaces with coherent accelerators Embodiments disclose techniques for enabling the use poll and select subroutines with coherent accelerator block or character devices. In one embodiment, an... |
| US-9,779,040 |
Portable device, system, and information processing apparatus A portable device includes: a first interface circuit configured to receive, from an information processing apparatus, device information of the information... |
| US-9,779,039 |
Impedance adjustment in a memory device Methods and apparatus for impedance adjustment operations in memory devices are disclosed. One such method includes adjusting an impedance of a particular... |
| US-9,779,038 |
Efficient suspend-resume operation in memory devices A method includes executing a first memory access operation in a memory. A progress indication, which is indicative of a progress of execution of the first... |
| US-9,779,037 |
Establishing connectivity of modular nodes in a pre-boot environment Various embodiments described herein provide for establishing connectivity of nodes by employing base management controllers associated with the nodes. For some... |
| US-9,779,036 |
Communication device, information processing method, and program A device may include a control unit to control determination of a processing mode of at least two processing modes and in which an application is executed. The... |
| US-9,779,035 |
Log-based data storage on sequentially written media Techniques for implementing a log-based storage scheme upon data storage devices are described herein. A data storage device is initialized by writing an... |
| US-9,779,034 |
Protection key management and prefixing in virtual address space legacy
emulation system A system is described to provide protection key access control in a system whose operating system and processor were not designed to provide a protection key... |
| US-9,779,033 |
Memory management device and non-transitory computer readable storage
medium In one embodiment, a storage unit stores a table tree and verifier tree. The table tree includes parent and child tables. The verifier tree includes parent and... |
| US-9,779,032 |
Protecting storage from unauthorized access Protecting contents of storage in a computer system from unauthorized access. The computer system includes one or more processing units sharing the storage.... |
| US-9,779,031 |
Caching policies for selection and replacement of objects In one embodiment, a computer-implemented method includes inserting a set of accessed objects into a cache, where the set of accessed objects varies in size. An... |
| US-9,779,030 |
Grouping tracks for destaging Various embodiments for grouping tracks for destaging by a processor device in a computing environment are provided. Tracks are selected for destaging from a... |
| US-9,779,029 |
Cache replacement policy for data with strong temporal locality Various cache replacement policies are described whose goals are to identify items for eviction from the cache that are not accessed often and to identify items... |
| US-9,779,028 |
Managing translation invalidation Managing translation invalidation includes: in response to determining that a first invalidation message (IM) applies to a subset of virtual addresses (VAs)... |
| US-9,779,027 |
Apparatus, system and method for managing a level-two cache of a storage
appliance Aspects of the present disclosure disclose systems and methods for managing a level-two persistent cache. In various aspects, a solid-state drive is employed as... |
| US-9,779,026 |
Cache bypass utilizing a binary tree A storage command is received at a block level interface from a file system. The storage command is associated with a window of a virtual drive. One of a... |
| US-9,779,025 |
Cache architecture for comparing data The present disclosure includes apparatuses and methods for a cache architecture. An example apparatus that includes a cache architecture according to the... |
| US-9,779,024 |
Semiconductor storage device and processor system A semiconductor storage device has a non-volatile memory, a memory controller to carry out write processing to the non-volatile memory using a write pulse, and... |
| US-9,779,023 |
Storing inline-compressed data in segments of contiguous physical blocks Techniques for storing data received by a data storage system involve performing inline compression on received data and storing resulting compressed data in... |
| US-9,779,022 |
Methods for caching and reading data to be programmed into a storage unit
and apparatuses using the same A method for caching and reading data to be programmed into a storage unit, performed by a processing unit, including at least the following steps. A write... |
| US-9,779,021 |
Non-volatile memory controller cache architecture with support for
separation of data streams A system according to one embodiment includes non-volatile memory, and a non-volatile memory controller having a cache. An architecture of the cache supports... |
| US-9,779,020 |
System and method for providing an address cache for memory map learning A system for interfacing with a co-processor or input/output device is disclosed. According to one embodiment, the system provides a one-hot address cache... |
| US-9,779,019 |
Data storage layout Examples of the present disclosure provide apparatuses and methods for determining a data storage layout. An example apparatus comprising a first address space... |
| US-9,779,018 |
Technique for quantifying logical space trapped in an extent store A technique quantifies logical storage space trapped in an extent store due to overlapping write requests associated with volume metadata managed by the volume... |
| US-9,779,017 |
Data storage device and data accessing method thereof A data storage device including a flash memory and a controller. The flash memory includes a plurality of dies having a plurality of columns, wherein each of... |
| US-9,779,016 |
Computing system with backup and recovery mechanism and method of
operation thereof An integrated circuit system, and a method of operation thereof, including: a memory unit having a volatile memory device with data and a non-volatile... |
| US-9,779,015 |
Oversubscribed storage extents with on-demand page allocation In response to receiving a write request directed to a particular logical block of a storage object, a page of free space (sufficient to accommodate the payload... |
| US-9,779,014 |
Resilient mock object creation for unit testing Embodiments of the invention provide for fault alerting in mock object supported unit testing. In a method for fault alerting in mock object supported unit... |
| US-9,779,013 |
Method and system for optimizing a test suite comprising plurality of test
cases The present disclosure relates to a method and system for optimizing a test suite comprising plurality of test cases. In an embodiment, the pluralities of test... |
| US-9,779,012 |
Dynamic and global in-system debugger The conventional debugger tool used to debug the Embedded System is limited to JTAG as the standard physical interface and also to specific processor. The... |
| US-9,779,011 |
Testing system The present invention relates to a testing system, including a testing host and a relay host, where the testing host may test a tested target, and a testing... |
| US-9,779,010 |
Registration-based remote debug watch and modify A remote debugging technique provides anonymity of program variables and selective debugging capability by providing a registration facility by which program... |
| US-9,779,009 |
Source code equivalence verification device and source code equivalence
verification method When verifying rapidly the equivalence between source codes with respect to refactoring, the present invention performs two types of verification: verification... |
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