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| Patent # | Description |
|---|---|
| US-9,786,579 |
Imaging device, imaging apparatus, production apparatus and method, and
semiconductor device There is provided an imaging device including a semiconductor having a light-receiving portion that performs photoelectric conversion of incident light,... |
| US-9,786,578 |
Orthogonally hinged individualized memory module cooling A memory module cooling system includes a liquid cooled manifold assembly and a heat spreader assembly rotateably attached to the liquid cooled manifold... |
| US-9,786,577 |
Power module substrate, heat-sink-attached power-module substrate, and
heat-sink-attached power module A power-module substrate including a circuit layer having a first aluminum layer bonded on one surface of a ceramic substrate and a first copper layer bonded on... |
| US-9,786,576 |
Positive-type photosensitive resin composition, method for production of
resist pattern, semiconductor device,... A positive-type photosensitive resin composition includes (A) a phenol resin modified by a compound having an unsaturated hydrocarbon group having 4 to 100... |
| US-9,786,575 |
Printed circuit module having semiconductor device with a polymer
substrate and methods of manufacturing the same A printed circuit module and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned... |
| US-9,786,574 |
Thin film based fan out and multi die package platform Thin film based fan out wafer level packaging and a method of manufacturing the same are disclosed. Embodiments include a method including forming tapered via... |
| US-9,786,573 |
Electronic component package An electronic component package includes: a core including a cavity, a first resin layer, a second resin layer and a reinforcing layer disposed between the... |
| US-9,786,572 |
Flip chip ball grid array with low impedance and grounded lid A contact spring for placement in a gap between an electrical substrate opposite a lid (electrically conductive heat spreader) of an electronic device comprises... |
| US-9,786,571 |
Test key Provided is a test key including a plurality of diffusion regions, a plurality of gate lines, a dielectric layer, a first comb structure and a second comb... |
| US-9,786,570 |
Methods for depositing films on sensitive substrates Methods and apparatus to form films on sensitive substrates while preventing damage to the sensitive substrate are provided herein. In certain embodiments,... |
| US-9,786,569 |
Overlay measurement and compensation in semiconductor fabrication A method includes receiving a device having a first layer and a second layer over the first layer, the first layer having a first overlay mark. The method... |
| US-9,786,568 |
Method of manufacturing an integrated circuit substrate A method of manufacturing a wafer. The method includes providing a wafer that includes a plurality of semiconductor device structures, and testing at least one... |
| US-9,786,567 |
Chip-on-wafer process control monitoring for chip-on-wafer-on-substrate
packages An embodiment method includes providing a standardized testing structure design for a chip-on-wafer (CoW) structure, wherein the standardized testing structure... |
| US-9,786,566 |
Aspect ratio for semiconductor on insulator A method comprises forming a first set of one or more fins in a first region from an insulated substrate and a second set of one or more fins in a second region... |
| US-9,786,565 |
Semiconductor device and method of manufacturing the semiconductor device A semiconductor device includes a transistor configuration including first and second gate electrodes, each of the first and second gate electrodes having at... |
| US-9,786,564 |
Semiconductor device and manufacturing method thereof A semiconductor device includes a substrate, a first gate, a second gate, and an insulating structure. The substrate includes a first fin and a second fin. The... |
| US-9,786,563 |
Fin pitch scaling for high voltage devices and low voltage devices on the
same wafer A semiconductor device is provided that includes a first plurality of fin structures having a first width in a first region of a substrate, and a second... |
| US-9,786,562 |
Method and device for cutting wafers A method is described of radiatively cutting a wafer, the method comprising the steps of low power cutting of two trenches followed by high power cutting of a... |
| US-9,786,561 |
Wafer processing method A wafer processing method for dividing a wafer into individual device chips along division lines is disclosed. The wafer processing method includes a back... |
| US-9,786,560 |
Semiconductor package structure having first and second guard ring regions
of different conductivity types and... A method for forming a semiconductor package structure is provided. The method for forming a semiconductor package structure includes providing a substrate,... |
| US-9,786,559 |
Process and material for preventing deleterious expansion of high aspect
ratio copper filled through silicon... Techniques are disclosed for forming through-silicon vias (TSVs) implementing a negative thermal expansion (NTE) material such as zirconium tungstate... |
| US-9,786,558 |
Semiconductor devices including a bit line structure and a contact plug Semiconductor devices are provided. A semiconductor device includes a bit line structure and a contact plug. The contact plug is adjacent a sidewall of the bit... |
| US-9,786,557 |
Two-dimensional self-aligned super via integration on self-aligned gate
contact Techniques relate to contacts for semiconductors. First gate contacts are formed on top of first gates, second gate contacts are on second gates, and terminal... |
| US-9,786,556 |
Semiconductor device and method of manufacturing the semiconductor device According to an embodiment, a manufacturing method of a semiconductor device includes forming, on a film to be processed, a plurality of first core material... |
| US-9,786,555 |
Method for reducing contact resistance Disclosed is a method for reducing contact resistance, including depositing a GST layer on an InGaAs substrate, generating an InGaAs/GST/Ni stacked structure by... |
| US-9,786,554 |
Self aligned conductive lines A method for forming conductive lines on a wafer comprises forming a first hardmask, a planarizing layer, a second hardmask, a layer of sacrificial mandrel... |
| US-9,786,553 |
Advanced BEOL interconnect structure containing uniform air gaps A semiconductor structure including a back-end-of-the-line (BEOL) interconnect structure that contains an air gap located on each side of an interconnect metal... |
| US-9,786,552 |
Methods of forming fine patterns including pad portion and line portion A method of forming fine patterns includes forming a partition on a base layer. The partition includes a partition block, a first open region provided to face... |
| US-9,786,551 |
Trench structure for high performance interconnection lines of different
resistivity and method of making same An integrated circuit includes a substrate with an interlevel dielectric layer positioned above the substrate. First trenches having a first depth are formed in... |
| US-9,786,550 |
Low resistance metal contacts to interconnects A semiconductor device and a method of fabricating a contact to interface with an interconnect in a semiconductor device are described. The device includes a... |
| US-9,786,549 |
Etch damage and ESL free dual damascene metal interconnect A method of forming a dual damascene metal interconnect for a semiconductor device. The method includes forming a layer of low-k dielectric, forming vias... |
| US-9,786,548 |
Methods of forming one or more covered voids in a semiconductor substrate Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for... |
| US-9,786,547 |
Channel silicon germanium formation method A method of making a channel region in a semiconductor device includes providing a substrate having a first transistor area arranged adjacent to a second... |
| US-9,786,546 |
Bulk to silicon on insulator device A method for forming a semiconductor device comprises forming a fin in a bulk semiconductor substrate and depositing a first insulator layer over portions of... |
| US-9,786,545 |
Method of forming ANA regions in an integrated circuit A method includes providing a structure having a first hardmask layer, interposer layer, second hardmask layer and mandrel layer disposed respectively over a... |
| US-9,786,544 |
Floating body memory cell apparatus and methods Some embodiments include apparatus and methods having a base; a memory cell including a body, a source, and a drain; and an insulation material electrically... |
| US-9,786,543 |
Isolation structure of semiconductor device The invention relates to an isolation structure of a semiconductor device and a method of forming. An exemplary isolation structure for a semiconductor device... |
| US-9,786,542 |
Mechanisms for forming semiconductor device having isolation structure Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate having an upper surface.... |
| US-9,786,541 |
Dicing sheet with protective film forming layer and chip fabrication
method A dicing sheet with a protective film forming layer has a substrate film, an adhesive layer, and a protective film forming layer, and at a minimum, the adhesive... |
| US-9,786,540 |
Method of manufacturing a semiconductor device A system and method for a semiconductor wafer carrier is disclosed. An embodiment comprises a semiconductor wafer carrier wherein conductive dopants are... |
| US-9,786,539 |
Wafer chuck A wafer chuck is provided. The wafer chuck includes a main body and a dielectric layer disposed over the main body. The wafer chuck also includes an electrode... |
| US-9,786,538 |
Attachment member and attachment device using the same An attachment member (1) according to an embodiment of the present invention includes: a base (4) composed of a ceramic sintered body, which has an annular part... |
| US-9,786,537 |
Wafer edge measurement and control Devices and methods are provided for positioning and/or rotating a substrate without solid contact, such as by floating the wafer on a thin layer of gas. Since... |
| US-9,786,536 |
Reticle rack system The present disclosure relates to semiconductor manufacturing, in particular to reticle rack systems. The teachings of the present disclosure may be embodied in... |
| US-9,786,535 |
Wafer transport system and method for operating the same The present invention relates to a wafer transport system and a method of operating the same. The wafer transport system comprises at least one semiconductor... |
| US-9,786,534 |
EFEM An EFEM 1 includes a wafer transfer chamber 3 having an interior space in which a wafer transfer robot 5 is disposed and load ports 2 disposed adjacent to a... |
| US-9,786,533 |
Substrate processing apparatus, substrate processing method and storage
medium Provided is a substrate processing apparatus which can efficiently transfer substrates using a conveying mechanism including a plurality of substrate holding... |
| US-9,786,532 |
Substrate processing apparatus and method of transferring a substrate A substrate processing apparatus is described herein. The substrate processing apparatus comprises a transferring device including: a grasping section... |
| US-9,786,531 |
Gas purge unit, load port apparatus, and installation stand for purging
container A gas purge unit includes an intake nozzle 28, a pivotable body 31, and an O-ring 35. The intake nozzle 28 has a nozzle opening 26 flowing out a cleaning gas.... |
| US-9,786,529 |
Pyrometry filter for thermal process chamber Embodiments of the invention generally relate to pyrometry during thermal processing of semiconductor substrates. More specifically, embodiments of the... |
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