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Patent # Description
US-9,793,233 Forming sacrificial composite materials for package-on-package architectures and structures formed thereby
Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a...
US-9,793,232 All intermetallic compound with stand off feature and method to make
A standoff structure for providing improved interconnects is provided, wherein the structure employs nickel copper alloy or copper structures having increased...
US-9,793,231 Under bump metallurgy (UBM) and methods of forming same
A device package includes a die, fan-out redistribution layers (RDLs) over the die, and an under bump metallurgy (UBM) over the fan-out RDLs. The UBM comprises...
US-9,793,230 Semiconductor structure and method of forming
A device package and methods of forming are provided. The device package includes a logic die and a first passivation layer over the logic die. The device...
US-9,793,229 Insulating protrusion in the trench of a re-distribution layer structure
A re-distribution layer structure is adapted to be disposed on a substrate having a pad and a protective layer which has a first opening exposing a part of the...
US-9,793,228 Semiconductor device and method of manufacturing the semiconductor device
Reliability of a semiconductor device is improved. A slope is provided on a side face of an interconnection trench in sectional view in an interconnection width...
US-9,793,227 Switchable die seal connection
An integrated circuit (IC) structure for radio frequency (RF) circuits having a multi-point selectably grounded die seal and multi-point selectably grounded...
US-9,793,226 Power supply transient performance (power integrity) for a probe card assembly in an integrated circuit test...
The present invention describes essentially three different embodiments for the implementation of low impedance (over frequency) power delivery to a die. Such...
US-9,793,225 Thermal expansion compensators for controlling microelectronic package warpage
The present description relates to the field of fabricating microelectronic packages, wherein a microelectronic device may be attached to a microelectronic...
US-9,793,223 Semiconductor package and method of manufacturing the same
There are provided a semiconductor package and a method of manufacturing the same. The semiconductor package includes: a substrate having a ground electrode...
US-9,793,222 Substrate designed to provide EMI shielding
Packages and packaging techniques for providing EMI shielding are described. In an embodiment, a package includes an electrically conductive ground structure on...
US-9,793,221 Semiconductor device mounting method
A first insulating film is applied onto a joining face of a semiconductor device including a connection terminal on a joining face, and the connection terminal...
US-9,793,220 Detection of environmental conditions in a semiconductor chip
A capacitive sensor and measurement circuitry is described that may be able to reproducibly measure miniscule capacitances and variations thereof. The...
US-9,793,219 Semiconductor element built-in wiring board and method for manufacturing the same
A wiring board includes a base substrate, a semiconductor element embedded in the substrate and having active and non-active surfaces such that the...
US-9,793,218 Method for manufacturing device embedded substrate, and device embedded substrate
In a method for manufacturing a device embedded substrate, a conductive via that penetrates a first insulating layer and a second insulating layer from an outer...
US-9,793,217 Package-on-package type semiconductor device which is realized through applying not a TSV technology but a...
A semiconductor device may include a bottom package embedded with a first semiconductor chip. The semiconductor device may include a middle package stacked over...
US-9,793,216 Fabrication of IC structure with metal plug
Aspects of the present disclosure include integrated circuit (IC) structures with metal plugs therein, and methods of forming the same. An IC fabrication method...
US-9,793,215 Semiconductor integrated circuit device
A semiconductor integratd circuit device includes fuse elements formed on an element isolation insulating film, and an insulating film, an interlayer insulating...
US-9,793,214 Heterostructure interconnects for high frequency applications
An integrated circuit includes an interconnect which includes a metal layer, a layer of graphene on at least one of the top surface of the interconnect or the...
US-9,793,213 Ion flow barrier structure for interconnect metallization
A method for forming an ion flow barrier between conductors includes forming a barrier material through a via in an interlevel dielectric layer and onto a first...
US-9,793,212 Interconnect structures and methods of forming same
An embodiment semiconductor device includes a first conductive feature in a dielectric layer and a second conductive feature over the dielectric layer and...
US-9,793,211 Dual power structure with connection pins
The present disclosure relates to an integrated chip having a dual power rail structure. In some embodiments, the integrated chip has a first metal interconnect...
US-9,793,210 Power line layout structure of semiconductor device and method for forming the same
A power line layout structure of a semiconductor device and a method for forming the same are disclosed. The power line layout structure of the semiconductor...
US-9,793,209 Semiconductor structures and fabrication method thereof
A method is provided for fabricating a semiconductor structure. The method includes providing a semiconductor substrate; forming an initial metal layer;...
US-9,793,208 Plasma discharge path
A semiconductor device with a temporary discharge path. During back-end-of-line (BEOL), the temporary discharge path discharges a plasma charge collected in a...
US-9,793,207 Electrical antifuse including phase change material
An antifuse structure including a first electrode that is present in at a base of the opening in the dielectric material. The antifuse structure further...
US-9,793,206 Heterogeneous metallization using solid diffusion removal of metal interconnects
A method for forming trenches of an interconnect network in a substrate. The method includes forming a first trench in the substrate, which has a first width....
US-9,793,204 Method of manufacturing semiconductor structure comprising plurality of through holes using metal hard mask
A method of manufacturing a semiconductor structure including a conductive structure, a dielectric layer, and a plurality of conductive features is disclosed....
US-9,793,203 Isolation device
An isolation device for isolating a first signal of a first circuit from a second circuit disclosed. The isolation device may have a substrate and a plurality...
US-9,793,202 Wireless apparatus
According to an embodiment, a wireless apparatus includes an interposer substrate, a semiconductor chip, a nonconductive layer, and a conductive film. The...
US-9,793,201 Glass clad microelectronic substrate
Embodiments of the present description relate to the field of fabricating microelectronic substrates. The microelectronic substrate may include a trace routing...
US-9,793,200 Printed wiring board
A printed wiring board includes a first circuit board having a first surface and a second surface on the opposite side with respect to the first surface, and a...
US-9,793,199 Circuit board with via trace connection and method of making the same
Various circuit boards and methods of manufacturing the same are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first...
US-9,793,198 Conductive connections, structures with such connections, and methods of manufacture
A solder connection may be surrounded by a solder locking layer (1210, 2210) and may be recessed in a hole (1230) in that layer. The recess may be obtained by...
US-9,793,197 Low profile leaded semiconductor package
In a semiconductor package a lead having a bottom surface coplanar with the flat bottom surface of the plastic body extends outward at the bottom of the...
US-9,793,196 Semiconductor device
Disclosed is a semiconductor device in which a resistance component resulting from wiring is reduced. A plurality of transistor units are arranged side by side...
US-9,793,195 Semiconductor device
A semiconductor device is disclosed. The semiconductor device has a semiconductor chip, an island having an upper surface to which the semiconductor chip is...
US-9,793,194 Leadframe
A leadframe includes an individual region to become a semiconductor device, and an outer frame part supporting the individual region through its peripheral...
US-9,793,193 Air gap and air spacer pinch off
Embodiments are directed to a method of forming a semiconductor device and resulting structures having an air spacer between a gate and a contact by forming a...
US-9,793,192 Formation of through via before contact processing
The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior...
US-9,793,191 Heat spreader with flexible tolerance mechanism
A semiconductor device packaging system includes a substrate, a heat spreader, a stiffener attached to the substrate, and at least one die electrically coupled...
US-9,793,190 Lid for integrated circuit package
A lid has a heat conductive substrate, a crystallized amorphous silicon layer and a native silicon oxide layer formed on the crystallized amorphous silicon...
US-9,793,189 Printed wiring board assembly, electrical device, and method for assembling printed wiring board assembly
A printed wiring board assembly includes a first board including a first surface; a second board including a second surface and facing the first surface; a...
US-9,793,188 Compositions and methods for semiconductor processing and devices formed therefrom
The present invention relates generally to the field of semiconductor devices, including solar cells, and compositions and methods for processing semiconductor...
US-9,793,187 3D packages and methods for forming the same
Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a method of forming a...
US-9,793,186 Semiconductor wafer and method of backside probe testing through opening in film frame
A semiconductor test system has a film frame including a tape portion with one or more openings through the tape portion. The opening is disposed in a center...
US-9,793,185 Test structure for monitoring liner oxidation
Embodiments of a method for forming a device using test structures are presented. The method includes providing a wafer with a device layer. The device layer...
US-9,793,184 Sensor for a semiconductor device
A semiconductor arrangement is presented. The semiconductor arrangement comprises a semiconductor body, the semiconductor body including a semiconductor drift...
US-9,793,183 System and method for measuring and improving overlay using electronic microscopic imaging and digital processing
An SEM image is acquired. The SEM image shows a metal line and a via hole disposed above the metal line. The via hole exposes a portion of the metal line...
US-9,793,182 Semiconductor device arrangement and a method for forming a semiconductor device arrangement
A semiconductor device arrangement includes a semiconductor substrate which includes a semiconductor substrate front side and a semiconductor substrate back...
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