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Patent # Description
US-9,793,181 Resistor calibration using a MOS capacitor
A method for calibrating a resistance value comprises the steps of measuring a value of a reference capacitor, and adjusting a variable resistor based on the...
US-9,793,180 Semiconductor device and manufacturing method thereof
A semiconductor device and manufacturing method thereof. Various aspects of the disclosure may, for example, comprise connection verification for a first one or...
US-9,793,179 Method for determining a bonding connection in a component arrangement and test apparatus
The application relates to a method for determining a bonding connection (1) in a component arrangement (2), wherein the method has the following steps:...
US-9,793,178 Focused beam scatterometry apparatus and method
The capacity to measure nanoscale features rapidly and accurately is of central importance for the monitoring of manufacturing processes in the production of...
US-9,793,177 Precise annealing of focal plane arrays for optical detection
Precise annealing of identified defective regions of a Focal Plane Array ("FPA") (e.g., exclusive of non-defective regions of the FPA) facilitates removal of...
US-9,793,176 Substrate processing apparatus and substrate processing method
The temperature of a chemical liquid supplied to a pot is detected while allowing a processing liquid discharge port to discharge the chemical liquid toward the...
US-9,793,175 FinFET devices having gate dielectric structures with different thicknesses on same semiconductor structure
FinFET devices are formed on the same semiconductor structure wherein at least one finFET device has a gate dielectric structure that is different in thickness...
US-9,793,174 FinFET device on silicon-on-insulator and method of forming the same
A fin field effect transistor (FinFET) on a silicon-on-insulator and method of forming the same are provided in the present invention. The FinFET includes first...
US-9,793,173 Semiconductor device and related manufacturing method
A semiconductor device may include a substrate, an n-channel field-effect transistor positioned on the substrate, and a p-channel field-effect transistor...
US-9,793,172 Reducing or eliminating pre-amorphization in transistor manufacture
A method for fabricating field effect transistors using carbon doped silicon layers to substantially reduce the diffusion of a doped screen layer formed below a...
US-9,793,171 Buried source-drain contact for integrated circuit transistor devices and method of making same
An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filled with a metal material to form a source (or...
US-9,793,170 Semiconductor device and fabrication method thereof
A semiconductor device includes a substrate, a first gate structure on the substrate, a first spacer adjacent to the first gate structure, a lower contact plug...
US-9,793,169 Methods for forming mask layers using a flowable carbon-containing silicon dioxide material
One method disclosed herein includes, among other things, forming a process layer on a substrate, forming a carbon-containing silicon dioxide layer above the...
US-9,793,168 Semiconductor structure with self-aligned wells and multiple channel materials
Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is...
US-9,793,167 Method for forming a wafer structure, a method for forming a semiconductor device and a wafer structure
A method of producing a semiconductor device and a wafer structure are provided. The method includes attaching a donor wafer comprising silicon carbide to a...
US-9,793,166 Lift-off method
A lift-off method for transferring an optical device layer in an optical device wafer to a transfer substrate, the optical device layer being formed on the...
US-9,793,165 Methods of fabricating semiconductor devices
A method of fabricating a semiconductor device is provided. The method may include preparing a substrate having a first surface and a second surface, forming a...
US-9,793,164 Self-aligned metal cut and via for back-end-of-line (BEOL) processes for semiconductor integrated circuit (IC)...
Self-aligned metal cut and via for Back-End-Of-Line (BEOL) processes for semiconductor integrated circuit (IC) fabrication, and related processes and devices,...
US-9,793,163 Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects
Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an...
US-9,793,162 Method for producing interconnections for 3D integrated circuit
Method for producing one or more connection elements for integrated circuit including the formation of sacrificial elements passing through a porous layer...
US-9,793,161 Methods for contact formation for 10 nanometers and beyond with minimal mask counts
A method of making a semiconductor device includes depositing a hard mask on a dielectric layer on a substrate, the dielectric layer being disposed around...
US-9,793,160 Aggressive tip-to-tip scaling using subtractive integraton
A method for forming an interconnect structure including: forming a semiconductor structure on a semiconductor substrate, the semiconductor structure having a...
US-9,793,159 Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects
Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, an interconnect structure for an...
US-9,793,158 Methods of fabricating a semiconductor device
A method of fabricating a semiconductor device, the method including forming at least one interconnection structure that includes a metal interconnection and a...
US-9,793,157 Etch stop for airgap protection
A semiconductor device that includes a gate structure on a channel region of a semiconductor device. Source and drain regions may be present on opposing sides...
US-9,793,156 Self-aligned low resistance metallic interconnect structures
Methods are provided for fabricating self-aligned, low resistance metal interconnect structures, as well as semiconductor devices comprising such metal...
US-9,793,155 Method of fabricating flash memory device
A method of fabricating a memory device includes forming an etching object layer and a lower sacrificial layer on a substrate, and forming an upper sacrificial...
US-9,793,154 Method for manufacturing bonded SOI wafer
The present invention is a method for manufacturing a bonded SOI wafer including: performing a thermal oxidation treatment including at least one of a thermal...
US-9,793,153 Low cost and mask reduction method for high voltage devices
Aspects of the present disclosure provides a device comprising a P-type semiconductor substrate, an N-type tub above the semiconductor substrate, a P-type...
US-9,793,152 Use of vacuum chucks to hold a wafer or wafer sub-stack
Techniques are described for holding a wafer or wafer sub-stack to facilitate further processing of the wafer of sub-stack. In some implementations, a wafer or...
US-9,793,151 Stiffener tape for electronic assembly
Some example forms relate to a stiffener tape for a wafer. The stiffener tape includes a mounting tape and a stiffener removably attached to the mounting tape....
US-9,793,150 Method for manufacturing semiconductor device
The present invention provides a manufacturing technique of a semiconductor device and a display device using a peeling process, in which a transfer process can...
US-9,793,149 Electrostatic clamping method and apparatus
A method of electrostatically clamping a dielectric wafer to a processing table during plasma processing is described. The table has interdigitated electrodes...
US-9,793,148 Method for positioning wafers in multiple wafer transport
A method for positioning wafers in dual wafer transport, includes: simultaneously moving first and second wafers placed on first and second end-effectors to...
US-9,793,146 Method of forming a cleanspace fabricator
A fab can be constructed as a round or rectangular annular tube with a primary cleanspace located in-between its inner and outer tubes. The fab can be encircled...
US-9,793,145 Support ring with encapsulated light barrier
Embodiments described herein provide a thermal processing apparatus with a heat source and a rotating substrate support opposite the heat source, the rotating...
US-9,793,144 Wafer holder and temperature conditioning arrangement and method of manufacturing a wafer
A wafer holder and temperature controlling arrangement has a metal circular wafer carrier plate, which covers a heater compartment. In the heater compartment a...
US-9,793,143 Semiconductor processing apparatus and method of operating the same
Embodiments of a semiconductor processing apparatus are provided. The semiconductor processing apparatus includes a housing and a support base disposed in the...
US-9,793,142 Substrate processing apparatus and substrate processing method
When a substrate W is processed, a cover member covers a peripheral portion of the upper surface of the substrate held by the substrate holding unit, and a...
US-9,793,141 Hybrid electronic device protected against humidity and method of protecting a hybrid electronic device against...
This method concerns the protection against humidity of a device including a first and a second electronic components respectively having two opposite surfaces,...
US-9,793,140 Staggered via redistribution layer (RDL) for a package and a method for forming the same
An embodiment staggered via redistribution layer (RDL) for a package includes a first polymer layer supported by a metal via. The first polymer layer has a...
US-9,793,139 Robust nucleation layers for enhanced fluorine protection and stress reduction in 3D NAND word lines
A silicon-containing nucleation layer can be employed to provide a self-aligned template for selective deposition of tungsten within backside recesses during...
US-9,793,138 Thermal processing method for wafer
The present invention relates to a thermal processing method for wafer. A wafer is placed in an environment filled with a non-oxygenated gas mixture comprising...
US-9,793,137 Use of grapho-epitaxial directed self-assembly applications to precisely cut logic lines
A method for patterning topography is provided. A substrate is provided with a plurality of lines. The method includes aligning and preparing a first directed...
US-9,793,136 Plasma etching method
A plasma etching method can form a hole having a required opening diameter in a silicon nitride layer, while suppressing a tip end portion of the hole from...
US-9,793,135 Method of cyclic dry etching using etchant film
A method for etching a target layer on a substrate by a dry etching process includes at least one etching cycle, wherein an etching cycle includes: depositing a...
US-9,793,134 Etching method
A method of concurrently etching a first region in which silicon oxide films and silicon nitride films are alternately stacked and a second region including the...
US-9,793,133 Methods of forming semiconductor device including capacitors with modified sidewalls and related devices
Methods of forming a semiconductor device can be provided by forming a first molding layer on a substrate and forming a first hole through the first molding...
US-9,793,132 Etch mask for hybrid laser scribing and plasma etch wafer singulation process
Etch masks and methods of dicing semiconductor wafers are described. In an example, an etch mask for a wafer singulation process includes a water-soluble matrix...
US-9,793,131 Pattern forming method using resist underlayer film
A pattern forming method which uses a resist underlayer film having resistance to a basic aqueous hydrogen peroxide solution. A pattern forming method...
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