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Patent # Description
US-9,806,225 Method of producing an optoelectronic semiconductor chip and an optoelectronic semiconductor chip
A method of producing an optoelectronic semiconductor chip includes providing a growth substrate and a semiconductor layer sequence grown on the growth...
US-9,806,224 Semiconductor layer sequence and method for producing a semiconductor layer sequence
A semiconductor layer sequence includes a first nitridic compound semiconductor layer, a second nitridic compound semiconductor layer, and an intermediate layer...
US-9,806,223 Optoelectronic semiconductor chip and method for the production thereof
A method for producing an optoelectronic semiconductor chip based on a nitride semiconductor system is specified. The method comprises the steps of: forming a...
US-9,806,221 Germanium photodetector with SOI doping source
Various particular embodiments include a method for forming a photodetector, including: forming a structure including a barrier layer disposed between a layer...
US-9,806,220 Metal foil metallization for backplane-attached solar cells and modules
A back contact solar cell is described which includes a semiconductor light absorbing layer; a first-level metal layer (M1), the M1 metal layer on a back side...
US-9,806,219 Displays with camera window openings
A display may include a color filter layer, a liquid crystal layer, and a thin-film transistor layer. A camera window may be formed in the display to...
US-9,806,218 Photodetector using bandgap-engineered 2D materials and method of manufacturing the same
A photodetector includes an insulating layer on a substrate, a first graphene layer on the insulating layer, a 2-dimensional (2D) material layer on the first...
US-9,806,217 Fully integrated CMOS-compatible photodetector with color selectivity and intrinsic gain
A metal-semiconductor-metal photodetecting device and method of manufacturing a metal-semiconductor-metal photodetecting device that includes a p-type silicon...
US-9,806,216 Semiconductor device for a system for measuring the temperature, and manufacturing method thereof
A semiconductor device for a system for measuring temperature, which includes a first UV detector and a second UV detector. The first and second UV detectors...
US-9,806,215 Encapsulated concentrated photovoltaic system subassembly for III-V semiconductor solar cells
A solar cell receiver subassembly for use in a concentrating solar system which concentrates the solar energy onto a solar cell by a factor of 1000 or more for...
US-9,806,214 Photovoltaic module with improved mechanical and electrical links
Photovoltaic module device (1) comprising a photovoltaic module (4) and an electrical connection element of a first type (2), characterized in that the...
US-9,806,213 Encapsulant for PV module, method of manufacturing the same and PV module comprising the same
The present application relates to an encapsulant for a PV module, a method of manufacturing the same and a PV module. The encapsulant according to an...
US-9,806,212 Ultrathin group II-VI semiconductor layers, group II-VI semiconductor superlattice structures, photovoltaic...
Disclosed are ultrathin layers of group II-VI semiconductors, group II-VI semiconductor superlattice structures, photovoltaic devices incorporating the layers...
US-9,806,211 Tandem solar cell with improved absorption material
A photosensitive device and method includes a top cell having an N-type layer, a P-type layer and a top intrinsic layer therebetween. A bottom cell includes an...
US-9,806,210 Photoelectric conversion element
A photoelectric conversion element includes a semiconductor, an intrinsic layer disposed on the semiconductor and containing hydrogenated amorphous silicon, a...
US-9,806,209 Passivated iron disulfide surface encapsulated in zinc sulfide
A passivated iron disulfide (FeS.sub.2) surface encapsulated by an epitaxial zinc sulfide (ZnS) capping layer or matrix is provided. Also disclosed are methods...
US-9,806,208 Method of passivating an iron disulfide surface via encapsulation in a zinc sulfide matrix
A method for passivating the surface of crystalline iron disulfide (FeS.sub.2) by encapsulating it within an epitaxial zinc sulfide (ZnS) matrix. Also disclosed...
US-9,806,207 Solar cell and method for manufacturing same
A solar cell includes a support substrate, a back electrode layer on the support substrate, a light absorbing layer on the back electrode layer, a buffer layer...
US-9,806,206 Optimized grid design for concentrator solar cell
Grid patterns for concentrator solar cells that increase power output are provided. In one aspect, a top contact for a solar cell is provided that includes: bus...
US-9,806,205 N-type aluminum nitride monocrystalline substrate
A silicon-doped n-type aluminum nitride monocrystalline substrate wherein, at a photoluminescence measurement at 23.degree. C., a ratio (I1/I2) between the...
US-9,806,204 Semiconductor devices
A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate...
US-9,806,203 Nonplanar III-N transistors with compositionally graded semiconductor channels
A III-N semiconductor channel is compositionally graded between a transition layer and a III-N polarization layer. In embodiments, a gate stack is deposited...
US-9,806,202 Semiconductor device and memory device
The present invention provides a transistor having a high on-state current. The transistor includes a plurality of fins, a first oxide semiconductor, a gate...
US-9,806,201 Semiconductor device
A method for forming an oxide that can be used as a semiconductor of a transistor or the like is provided. In particular, a method for forming an oxide with...
US-9,806,200 Semiconductor device
A semiconductor device including a miniaturized transistor is provided. The semiconductor device includes a first insulator, a second insulator, a...
US-9,806,199 Thin film transistor, array substrate and display device having the same, and method of manufacturing thereof
The disclosure provides a method of manufacturing a thin film transistor on a base substrate by patterning an active layer comprising a metal oxynitride, and...
US-9,806,198 Semiconductor device and method for manufacturing the same
Objects are to obtain a minute transistor by reducing the channel length L of a transistor used in a semiconductor integrated circuit such as an LSI, a CPU, or...
US-9,806,197 Display device having back gate electrodes
A display device including a substrate, a first gate electrode, a second gate electrode, an active layer, and a first data electrode is provided. The active...
US-9,806,196 Semiconductor device with fin and related methods
A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel...
US-9,806,195 Method for fabricating transistor with thinned channel
A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The...
US-9,806,194 FinFET with fin having different Ge doped region
A semiconductor device is provided. A fin is disposed on a substrate. The fin, including a first material and a second material, includes a first fin area and a...
US-9,806,193 Stress in trigate devices using complimentary gate fill materials
Embodiments relate to an improved tri-gate device having gate metal fills, providing compressive or tensile stress upon at least a portion of the tri-gate...
US-9,806,192 Suppression of back-gate transistors in RF CMOS switches built on an SOI substrate
The present disclosure relates to a silicon-on-insulator (SOI) substrate structure with a buried dielectric layer for radio frequency (RF) complementary...
US-9,806,191 Vertical channel oxide semiconductor field effect transistor and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a source layer; removing part of the source layer to...
US-9,806,189 Semiconductor device
A semiconductor device includes a first conductivity type semiconductor layer, a second conductivity type body region in a semiconductor layer surface portion,...
US-9,806,188 Method for producing a controllable semiconductor component having trenches with different widths and depths
A controllable semiconductor component is produced by providing a semiconductor body with a top side and a bottom side, and forming a first trench protruding...
US-9,806,187 Method for manufacturing a semiconductor device
A method for forming a semiconductor device is provided. The method includes providing a semiconductor body with a horizontal surface. An epitaxy hard mask is...
US-9,806,186 Termination region architecture for vertical power transistors
A vertical power switching device, such as a vertical superjunction metal-oxide-semiconductor field-effect-transistor (MOSFET), in which termination structures...
US-9,806,185 Non-volatile memory device and method of manufacturing the same
A non-volatile memory device and a method of manufacturing the same are provided. The device includes a substrate including a cell region and a peripheral...
US-9,806,184 Semiconductor device with low-conducting field-controlling element
A semiconductor device including a low conducting field-controlling element is provided. The device can include a semiconductor including an active region...
US-9,806,183 Stress control on thin silicon substrates
Methods for stress control in thin silicon (Si) wafer-based semiconductor materials. By a specific interrelation of process parameters (e.g., temperature,...
US-9,806,182 Parasitic channel mitigation using elemental diboride diffusion barrier regions
III-nitride materials are generally described herein, including material structures comprising III-nitride material regions and silicon-containing substrates....
US-9,806,181 Insulated gate power device using a MOSFET for turning off
An insulated gate turn-off (IGTO) device has a PNPN layered structure so that vertical NPN and PNP transistors are formed. Trench gates are formed extending...
US-9,806,180 Forming a non-planar transistor having a quantum well channel
In one embodiment, the present invention includes an apparatus having a substrate, a buried oxide layer formed on the substrate, a silicon on insulator (SOI)...
US-9,806,179 Method for fabricating conducting structure and thin film transistor array panel
A method of providing a conducting structure over a substrate, which comprises: disposing a lower sub-layer over a substrate, the lower sub-layer comprising a...
US-9,806,178 FinFET structure and method for fabricating the same
A method comprises recessing a substrate to form a fin enclosed by an isolation region, wherein the substrate is formed of a first semiconductor material,...
US-9,806,177 FinFETs and methods for forming the same
A FinFET includes a semiconductor fin including an inner region, and a germanium-doped layer on a top surface and sidewall surfaces of the inner region. The...
US-9,806,176 Structure and method for defect passivation to reduce junction leakage for finfet device
The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate of a first...
US-9,806,175 Power MOSFET device structure for high frequency applications
This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near...
US-9,806,174 Double-resurf LDMOS with drift and PSURF implants self-aligned to a stacked gate "bump" structure
A double-RESURF LDMOS transistor has a gate dielectric structure including a shallow field "bump" oxide region and an optional raised dielectric structure that...
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