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Patent # Description
US-9,806,122 Visible and infrared image sensor
A pixel array including an Si.sub.xGe.sub.y layer disposed on a first semiconductor layer. A plurality of pixels is disposed in the first semiconductor layer....
US-9,806,120 Solid-state image pickup apparatus and electronic apparatus
A solid-state image pickup apparatus includes a pixel region in which a plurality of pixels each including a photoelectric conversion element are arranged,...
US-9,806,119 3DIC seal ring structure and methods of forming same
A semiconductor device includes a first semiconductor chip including a first substrate, a plurality of first dielectric layers and a plurality of conductive...
US-9,806,118 Solid-state imaging device, manufacturing method thereof, and electronic apparatus
A solid-state imaging device includes a plurality of photoelectric conversion portions each provided to correspond to each of a plurality of pixels in a...
US-9,806,117 Biased deep trench isolation
An image sensor includes a plurality of photodiodes disposed in a semiconductor material, and a through-semiconductor-via coupled to a negative voltage source....
US-9,806,116 Complementary metal grid and deep trench isolation in CIS application
A CMOS image sensor structure includes a substrate and pixel portions. Each pixel portion includes intersection areas, the border areas each of which is located...
US-9,806,115 Image sensor with inner light-condensing scheme
An image sensor may include: a photoelectric conversion layer suitable for converting light into an electrical signal; a spacer layer formed over the...
US-9,806,114 Solid-state imaging device, method of manufacturing solid-state imaging device, and electronic apparatus
A solid-state imaging device includes pixels each having a photoelectric conversion element for converting incident light to an electric signal, color filters...
US-9,806,113 CMOS image sensors including vertical transistor
Provided is a complementary metal-oxide-semiconductor (CMOS) image sensor. The CMOS image sensor can include a substrate having a first device isolation layer...
US-9,806,112 Electrostatic discharge guard structure
The present application provides an electrostatic discharge guard structure for photonic platform based photodiode systems. In particular this application...
US-9,806,111 Nanostructure optoelectronic device with independently controllable junctions
Nanostructure array optoelectronic devices are disclosed. The optoelectronic device may have one or more intermediate electrical contacts that are physically...
US-9,806,110 Pixel structure, LCD panel, and manufacturing method thereof
An embodiment of the disclosed technology provides a pixel structure, comprising a TFT, a reflective region and a transmissive region, wherein the reflective...
US-9,806,109 Half tone mask plate and method for manufacturing array substrate using the same
The present disclosure provides a half tone mask plate used to manufacture an active layer pattern as well as a source electrode pattern, a drain electrode...
US-9,806,108 Manufacturing method of thin film transistor, manufacturing method of array substrate and array substrate
A manufacturing method of a thin film transistor, a manufacturing method of an array substrate and an array substrate are provided. The manufacturing method of...
US-9,806,107 Semiconductor device
Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors....
US-9,806,106 Thin film transistor array substrate and manufacture method thereof
The present invention provides a thin film transistor array substrate and a manufacture method thereof, comprising: a substrate (1) and a thin film transistor...
US-9,806,105 Thin film transistor substrate, display device including a thin film transistor substrate, and method of...
Provided are a thin film transistor (TFT) substrate, a display device, and a method of forming the TFT. A TFT substrate includes: a first TFT including: a...
US-9,806,104 Display device and manufacturing method thereof
According to one embodiment, a display device includes a first substrate including a first insulative substrate, an outer peripheral wiring formed above the...
US-9,806,103 Array substrates, methods for fabricating the same, and display device containing the same
The present disclosure provides a method for fabricating an array substrate. The method includes providing a substrate; forming a first pattern on the substrate...
US-9,806,102 Display substrate and method for fabricating the same and display device
A display substrate, a method for fabricating the same, and a display device are disclosed. The display substrate comprises a plurality of pixels; and a...
US-9,806,101 Pixel array having strip-shaped electrodes, display panel, and display device
The present invention provides a pixel array, a display panel and a display device, and the pixel array includes a plurality of gate lines and a plurality of...
US-9,806,100 Manufacturing method of thin film transistor array panel and thin film transistor array panel
A manufacturing method of a thin film transistor array panel according to an exemplary embodiment of the present invention includes forming an amorphous silicon...
US-9,806,099 Semiconductor device
A semiconductor device including a capacitor whose charge capacity is increased while improving the aperture ratio is provided. Further, a semiconductor device...
US-9,806,098 Light-emitting device
To provide a light-emitting device capable of suppressing the display of an afterimage. A plurality of pixels arranged in n rows and m columns (n and m are each...
US-9,806,097 Metal oxide semiconductor thin film, thin film transistor, and their fabricating methods, and display apparatus
A metal oxide semiconductor thin film, a thin film transistor (TFT), methods for fabricating the metal oxide semiconductor thin film and the TFT, and a display...
US-9,806,096 Semiconductor device and method for manufacturing the same
An object of the present invention is to prevent the deterioration of a TFT (thin film transistor). The deterioration of the TFT by a BT test is prevented by...
US-9,806,095 High voltage three-dimensional devices having dielectric liners
High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are...
US-9,806,094 Non-uniform spacing in transistor stacks
Field effect transistor stacks include a first field-effect transistor having a source finger, a drain finger, and a gate finger interposed therebetween, the...
US-9,806,093 Through-memory-level via structures for a three-dimensional memory device
A three dimensional NAND memory device includes word line driver devices located on or over a substrate, an alternating stack of word lines and insulating...
US-9,806,092 Semiconductor memory device and methods for manufacturing the same
According to one embodiment, a semiconductor memory device includes first to fourth conductive layers, a first intermediate insulating layer, a second...
US-9,806,091 Semiconductor memory device
A semiconductor memory device according to an embodiment comprises: a plurality of control gate electrodes arranged in a first direction intersecting an upper...
US-9,806,090 Vertical floating gate NAND with selectively deposited ALD metal films
A method of making a monolithic three dimensional NAND string which contains a semiconductor channel and a plurality of control gate electrodes, includes...
US-9,806,089 Method of making self-assembling floating gate electrodes for a three-dimensional memory device
Metal floating gate electrodes can be formed for a three-dimensional memory device by forming a memory opening having lateral recesses at levels of spacer...
US-9,806,088 Semiconductor memory device having memory cells arranged three-dimensionally and method of manufacturing the same
A semiconductor memory device includes a substrate, a plurality of insulating layers and wiring layers that are alternately formed, and a plurality of first...
US-9,806,087 Low cost high performance EEPROM device
Devices and methods for forming a device are presented. The method includes providing a substrate prepared with a cell area separated by other active areas by...
US-9,806,085 Semiconductor device and method of forming the same
The present invention provides a semiconductor device and a method of forming the same, and the semiconductor device includes a first insulating layer, a source...
US-9,806,084 Anti-fuse with reduced programming voltage
A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor...
US-9,806,083 Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance,...
Static random access memory (SRAM) bit cells with wordlines on separate metal layers for increased performance are disclosed. In one aspect, an SRAM bit cell is...
US-9,806,082 Semiconductor memory device including a sense amplifier on a semiconductor substrate, a memory cell including a...
According to one embodiment, a semiconductor memory device includes a sense amplifier on a semiconductor substrate, a memory cell array including a memory cell...
US-9,806,081 Semiconductor device having sub-cell blocks
A semiconductor device includes a substrate with cell and peripheral regions and capacitors provided on the cell region. The cell region may include a plurality...
US-9,806,080 Semiconductor devices and methods of manufacturing the same
A semiconductor device includes a substrate, a memory structure and a capacitor structure including at least one array of capacitors. The memory structure is...
US-9,806,079 Semiconductor device
The semiconductor device includes: a transistor having an oxide semiconductor layer; and a logic circuit formed using a semiconductor material other than an...
US-9,806,078 FinFET spacer formation on gate sidewalls, between the channel and source/drain regions
FinFET spacer formation includes, for example, providing an intermediate semiconductor structure having a substrate having one or more fin having a first and a...
US-9,806,077 Semiconductor structure with low defect and method for forming the same
A semiconductor structure and a method for forming the same are provided. The method for manufacturing a semiconductor structure includes forming a fin...
US-9,806,076 FinFET device and method of manufacturing same
A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin...
US-9,806,075 Integrated circuit devices having a Fin-type active region and methods of manufacturing the same
Integrated circuit devices include a substrate including first and second fin-type active regions and first and second gate structures. The first gate structure...
US-9,806,074 High voltage multiple channel LDMOS
An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a...
US-9,806,073 Electronic circuits including diode-connected bipolar junction transistors
A diode-connected bipolar junction transistor includes a common collector region of a first conductivity, a common base region of a second conductivity disposed...
US-9,806,072 Super CMOS devices on a microelectronics system
This application is directed to a low cost IC solution that provides Super CMOS microelectronics macros. Hereinafter, SCMOS refers to Super CMOS and Schottky...
US-9,806,071 Integrated circuit with elongated coupling
An integrated circuit comprises a first layer on a first level. The first layer comprises a set of first lines. The first lines each have a length and a width....
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