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Patent # Description
US-9,806,018 Copper interconnect structures
Semiconductor devices include a patterned dielectric layer overlaying a semiconductor substrate; a metal layer comprising copper disposed in the patterned...
US-9,806,017 Flip-chip, face-up and face-down centerbond memory wirebond assemblies
A microelectronic assembly can include a substrate having first and second surfaces and an aperture extending therebetween, the substrate having terminals. The...
US-9,806,016 Stretchable semiconductor packages and semiconductor devices including the same
A semiconductor package includes an extendible molding member, a chip embedded in the molding member to have a warped shape, and connectors disposed in the...
US-9,806,015 Semiconductor packages including through mold ball connectors on elevated pads and methods of manufacturing the...
A semiconductor package includes first bump pads on a first surface of an interconnection structure layer, elevated pads thicker than the first bump pads on the...
US-9,806,014 Interposer with beyond reticle field conductor pads
Various interposers and methods of manufacturing related thereto are disclosed. In one aspect, an apparatus is provided that includes an interposer that has a...
US-9,806,013 Multilayer structure for a semiconductor device and a method of forming a multilayer structure for a...
A multilayer structure for a semiconductor device and a method of forming a multilayer structure for a semiconductor device. The multilayer structure comprises:...
US-9,806,012 IC carrier of semiconductor package and manufacturing method thereof
The present invention discloses an IC Carrier of a semiconductor package and its manufacturing method. The IC Carrier of the semiconductor package includes a...
US-9,806,011 Non-uniform substrate stackup
Some embodiments described herein include apparatuses and methods of forming such apparatuses. One such embodiment may include a routing arrangement having pads...
US-9,806,010 Package module and method of fabricating the same
A method of fabricating a package module includes placing a pin frame having plural pins on a circuit substrate; bonding the pins to corresponding bonding areas...
US-9,806,009 Semiconductor device and power converter using the same
To suppress a temperature rise of a chip accompanying a production of large output by a power converter, and to reduce a size of the power converter. A power...
US-9,806,008 Clip based semiconductor package for increasing exposed leads
A semiconductor package includes a leadframe having a clip foot portion, the clip foot portion having a first tie bar, a conductive clip situated over the...
US-9,806,007 Semiconductor device manufacturing method
A semiconductor device manufacturing method which enhances the reliability of a semiconductor device. The method includes a step in which a source wire is...
US-9,806,006 Etch isolation LPCC/QFN strip
Various structures and fabrication methods for leadless plastic chip carrier (QFN) packages which utilize carriers in strip format, wherein the leads (or...
US-9,806,005 Electronic element mounting substrate and electronic device
An electronic element mounting substrate includes: a first wiring substrate configured to be a frame defining an interior portion as a first through-hole, the...
US-9,806,004 Semiconductor devices having a TSV, a front-side bumping pad, and a back-side bumping pad
Semiconductor devices are provided. The semiconductor devices include a substrate, a first interlayer insulating layer disposed on a front-side of the...
US-9,806,003 Single base multi-floating surface cooling solution
An apparatus including a primary device and at least one secondary device coupled to a substrate; a heat exchanger disposed on the primary device and on the at...
US-9,806,002 Multi-reference integrated heat spreader (IHS) solution
Methods, systems, and apparatuses that assist with cooling semiconductor packages, such as multi-chip packages (MCPs) are described. A semiconductor package...
US-9,806,001 Chip-scale packaging with protective heat spreader
A semiconductor package can include a semiconductor die having an integrated circuit, a first die surface, and an opposite second die surface. A packaging can...
US-9,806,000 Semiconductor device and manufacturing method of semiconductor device
A bonding member is a member shaped in a sheet and made of electrically-insulating resin. A semiconductor module includes a heatsink and a cooler that are...
US-9,805,999 Cured product
The present application relates to a cured product and the use thereof. The cured product has excellent processability, workability, and adhesive properties or...
US-9,805,998 Liquid sealing material and electronic component using same
The purpose of the present invention is to provide: a liquid sealing material which has excellent PCT (pressure cooker test) resistance; and an electronic...
US-9,805,997 Packaging methods for semiconductor devices with encapsulant ring
Packaging methods for semiconductor devices, and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device...
US-9,805,996 Substrate structure and manufacturing method thereof
A substrate structure and a manufacturing method thereof are provided. The substrate structure comprises a dielectric material layer, a conductive wiring layer,...
US-9,805,995 Element-accommodating package and mounting structure
An element-accommodating package which can improve frequency characteristics of an element-accommodating package having a coaxial connector, and a mounting...
US-9,805,994 Mesh-style NCEM pads, and process for making semiconductor dies, chips, and wafers using in-line measurements...
Wafers, chips, or dies that contain fill cells with structures configured to obtain in-line data via non-contact electrical measurements ("NCEM"). Such...
US-9,805,993 Device for determining the temperature of a substrate
An apparatus and a method for determining the temperature of a substrate, in particular of a semiconductor substrate during the heating thereof by means of at...
US-9,805,992 Strained finFET device fabrication
A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a...
US-9,805,991 Strained finFET device fabrication
A method for forming a fin on a substrate comprises patterning and etching a layer of a first semiconductor material to define a strained fin, depositing a...
US-9,805,990 FDSOI voltage reference
An integrated circuit having a reference device and method of forming the same. A reference device is disclosed having: a fully depleted n-type MOSFET...
US-9,805,989 Sacrificial cap for forming semiconductor contact
A method for forming a semiconductor device includes forming a fins on a substrate, forming a sacrificial gate stack over a channel region of the fins, a...
US-9,805,988 Method of forming semiconductor structure including suspended semiconductor layer and resulting structure
One aspect of the disclosure is directed to a method of forming a semiconductor structure including: forming a fin over a substrate within a device region, the...
US-9,805,987 Self-aligned punch through stopper liner for bulk FinFET
A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins...
US-9,805,986 High mobility transistors
An integrated circuit containing an n-channel finFET and a p-channel finFET has a dielectric layer over a silicon substrate. The fins of the finFETs have...
US-9,805,985 Method of manufacturing semiconductor device and semiconductor device
A method of manufacturing a semiconductor device includes removing a first gate among a plurality of gates over a substrate. Removing the first gate exposes a...
US-9,805,984 FinFET device
The present disclosure provides many different embodiments of a FinFET device that provide one or more improvements over the prior art. In one embodiment, a...
US-9,805,983 Multi-layer filled gate cut to prevent power rail shorting to gate structure
A method of forming a power rail to semiconductor devices that includes forming a gate structure extending from a first active region to a second active region...
US-9,805,982 Apparatus and method of adjusting work-function metal thickness to provide variable threshold voltages in finFETs
A method of adjusting work-function metal thickness includes providing a structure having a substrate, the substrate including a longitudinally extending array...
US-9,805,981 Semiconductor device
An object of the present invention is to improve the reliability of a semiconductor device. A semiconductor device has a first lead group comprised of a...
US-9,805,980 Method of manufacturing a semiconductor device
A semiconductor device manufacturing method comprising the steps of providing a matrix substrate having a main surface with plural device areas formed thereon,...
US-9,805,979 Electronic package and fabrication method thereof
An electronic package is provided, which includes: an electronic element having an active surface with a plurality of electrode pads, an inactive surface...
US-9,805,978 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes: forming a resist separation layer on a first main surface of a SiC substrate; applying a resist...
US-9,805,977 Integrated circuit structure having through-silicon via and method of forming same
One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include a front side and back side opposing the...
US-9,805,976 Co or Ni and Cu integration for small and large features in integrated circuits
In one embodiment of the present disclosure, a method for depositing metal in a feature on a workpiece is provided. The method includes electrochemically...
US-9,805,975 Thin-film transistor array substrate including gate-underlying stepped layer and etch-stopper, and organic...
A thin-film transistor (TFT) array substrate includes a substrate, a gate-underlying stepped layer disposed on the substrate, a gate electrode disposed on the...
US-9,805,974 Selective deposition of metallic films
Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic...
US-9,805,973 Dual silicide liner flow for enabling low contact resistance
A method for fabricating a semiconductor device includes depositing a sacrificial liner in self-aligned contact openings in first and second regions. The...
US-9,805,972 Skip via structures
The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a...
US-9,805,971 Method of forming a via contact
Semiconductor device and method for forming a semiconductor device are presented. The method includes providing a substrate having a device component with a...
US-9,805,970 Method for forming deep trench spacing isolation for CMOS image sensors
A method for manufacturing an image sensor with deep trench spacing isolation is provided. A trench is formed in a semiconductor substrate, around and between a...
US-9,805,968 Vertical structure having an etch stop over portion of the source
According to an exemplary embodiment, a method of forming a semiconductor device is provided. The method includes: providing a vertical structure over a...
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