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| Patent # | Description |
|---|---|
| US-9,825,051 |
Three dimensional NAND device containing fluorine doped layer and method
of making thereof A method of making a monolithic three dimensional NAND string comprising forming a stack of alternating layers of a first material and a second material... |
| US-9,825,050 |
Semiconductor device and manufacturing method thereof A semiconductor device whose performance is improved is disclosed. In the semiconductor device, an offset spacer formed in a memory cell is formed by a... |
| US-9,825,049 |
Semiconductor device and manufacturing method of semiconductor device A semiconductor device of the present invention has a first insulating film formed between a control gate electrode and a semiconductor substrate and a second... |
| US-9,825,048 |
Process for word line connections in 3D memory A 3D memory has multiple memory layers stacked on top of a substrate. Word lines in different memory layers are connected respectively to different columns of... |
| US-9,825,047 |
3-D structured non-volatile memory device and method of manufacturing the
same A non-volatile memory device according to an aspect of the present disclosure includes a substrate, a plurality of word lines stacked over the substrate and... |
| US-9,825,046 |
Flash memory device having high coupling ratio A flash memory cell structure includes a semiconductor substrate, a pad dielectric layer, a floating gate, a control gate, and a blocking layer. The pad... |
| US-9,825,045 |
Nonvolatile memory device A nonvolatile memory device includes a substrate including a device isolation layer defining an active region, a floating gate and a selection gate arranged... |
| US-9,825,044 |
Method to prevent lateral epitaxial growth in semiconductor devices The method for preventing epitaxial growth in a semiconductor device begins with cutting a set of long fins into a set of fins of a FinFET structure, the set of... |
| US-9,825,043 |
Semiconductor devices and methods of manufacture thereof A method of forming an SRAM cell includes forming a first vertical pull-down transistor, a second vertical pull-down transistor, a first vertical pass-gate... |
| US-9,825,042 |
Semiconductor memory device and method for driving the same In a conventional DRAM, when the capacitance of a capacitor is reduced, an error of reading data easily occurs. A plurality of cells are connected to one bit... |
| US-9,825,041 |
Integrated circuit structure with insulated memory device and related
methods Various embodiments include methods and integrated circuit (IC) structures. In some cases, an IC can include: a substrate; a deep trench within the substrate; a... |
| US-9,825,040 |
Semiconductor arrangement with capacitor and method of fabricating the
same A semiconductor arrangement includes an active region including a semiconductor device. The semiconductor arrangement includes a capacitor. The capacitor... |
| US-9,825,039 |
Semiconductor device and fabrication method thereof A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a semiconductor body, a first doped region, a second... |
| US-9,825,038 |
Semiconductor device To provide a semiconductor memory device which can be manufactured with high yield and which can achieve higher integration. A pair of memory cells adjacent to... |
| US-9,825,037 |
Semiconductor device and driving method thereof A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which... |
| US-9,825,036 |
Structure and method for semiconductor device A semiconductor device and methods of forming the same are disclosed. The semiconductor device comprises a substrate; an isolation structure over the substrate;... |
| US-9,825,035 |
Integrated circuit having a vertical power MOS transistor A device includes a vertical transistor comprising a first buried layer over a substrate, a first well over the first buried layer, a first gate in a first... |
| US-9,825,034 |
Semiconductor device and method of fabricating the same A semiconductor device may include a strain relaxed buffer layer provided on a substrate to contain silicon germanium, a semiconductor pattern provided on the... |
| US-9,825,033 |
Semiconductor devices and methods of manufacturing the same An integrated circuit device includes a substrate including a first region and a second region, a first transistor in the first region, the first transistor... |
| US-9,825,032 |
Metal layer routing level for vertical FET SRAM and logic cell scaling Methods of forming a VFET SRAM or logic device having a sub-fin level metal routing layer connected to a gate of one transistor pair and to the bottom S/D of... |
| US-9,825,031 |
Methods of forming a high-k contact liner to improve effective via
separation distance and the resulting devices A method includes forming first and second contact openings in a first dielectric layer. At least the first contact opening is at least partially lined with a... |
| US-9,825,030 |
High quality deep trench oxide An integrated circuit including a trench in the substrate with a high quality trench oxide grown on the sidewalls and the bottom of the trench where the ratio... |
| US-9,825,029 |
Discrete capacitor and manufacturing method thereof A discrete capacitor of the present invention includes a substrate having a front surface portion, an impurity diffusion layer formed on the front surface... |
| US-9,825,028 |
Ultra linear high voltage resistors Some embodiments include a resistor that may be used in audio conversion for an ADC. The resistor may be made up of an n-well as well as a p-well polysilicons.... |
| US-9,825,027 |
Semiconductor device A semiconductor device has a plurality of transistors, which have first electrodes in first trenches, and includes: two second trenches, which are formed side... |
| US-9,825,026 |
Semiconductor device and semiconductor circuit including the semiconductor
device with enhanced current-voltage... A semiconductor device is disclosed. The semiconductor device includes a substrate and a plurality of devices on the substrate, wherein a first device of the... |
| US-9,825,025 |
Semiconductor device and method of manufacturing semiconductor device A semiconductor device includes a first drain region that is made primarily of SiC, a drift layer, a channel region, a first source region, a source electrode... |
| US-9,825,024 |
Semiconductor device A semiconductor device is provided. The semiconductor device includes an active region, a gate line, a first metal interconnect, a power rail, and a second... |
| US-9,825,023 |
Insulated gate bipolar transistor comprising negative temperature
coefficient thermistor An embodiment of an IGBT comprises an emitter terminal at a first surface of a semiconductor body. The IGBT further comprises a collector terminal at a second... |
| US-9,825,022 |
ESD clamp circuit An ESD clamp circuit includes a power supply, a ground supply, an ESD detection transistor, a capacitor having a first terminal connected to the power supply... |
| US-9,825,021 |
Semiconductor device for electrostatic discharge protection A semiconductor device includes a substrate, a gate positioned on the substrate, a drain region and a source region formed at respective two sides of the gate... |
| US-9,825,020 |
Semiconductor device and an integrated circuit comprising an ESD
protection device, ESD protection devices and... A semiconductor device is provided which comprises an ESD protection device. The structure of the semiconductor device comprises a p-doped isolated region in... |
| US-9,825,019 |
Semiconductor device A semiconductor device includes a semiconductor layer of a first conductivity type, and first and second electrodes on the layer. A first region of the first... |
| US-9,825,018 |
Integrated circuit containing first and second DOEs of standard cell
compatible, NCEM-enabled fill cells, with... An IC includes first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain... |
| US-9,825,017 |
Method for manufacturing semiconductor device To improve the assemblability of a semiconductor device. When a memory chip is mounted over a logic chip, a recognition range including a recognition mark... |
| US-9,825,016 |
Light emitting device package A light emitting device package includes a cell array including a plurality of semiconductor light emitting units, and having a first surface and a second... |
| US-9,825,015 |
Light-mixing multichip package structure A light-mixing multichip package structure includes a circuit substrate, a first light-emitting module, a first package body, a second light-emitting module and... |
| US-9,825,014 |
Light source module, display panel, and display apparatus including the
same A light source module includes a circuit board having a plurality of chip mounting regions, the plurality of chip mounting regions respectively having at least... |
| US-9,825,013 |
Transfer-bonding method for the light emitting device and light emitting
device array A light emitting device array including a circuit substrate and a plurality of device layers is provided. The circuit substrate includes a plurality of bonding... |
| US-9,825,012 |
Light-emitting device A light-emitting device of an embodiment of the present application comprises light-emitting units; a transparent structure having cavities configured to... |
| US-9,825,011 |
Light emitting element and light emitting element array A light emitting element includes a semiconductor including an active layer, and a planar shape of the light emitting elements including a concave polygon. The... |
| US-9,825,010 |
Stacked chip package structure and manufacturing method thereof A stacked chip package structure includes a first chip, pillar bumps, a first encapsulant, a first redistribution layer, a second chip, a second encapsulant, a... |
| US-9,825,009 |
Interconnect substrate having cavity for stackable semiconductor assembly,
manufacturing method thereof and... An interconnect substrate having vertical connection channels around a cavity is characterized in that contact pads are exposed from the cavity and the vertical... |
| US-9,825,008 |
Package-on-package device with supplemental underfill and method for
manufacturing the same A method of forming a semiconductor device includes the following operations: (i) receiving a precursor package including a precursor substrate and a plurality... |
| US-9,825,007 |
Chip package structure with molding layer and method for forming the same A chip package structure is provided. The chip package structure includes a first chip, a second chip, and a third chip. The second chip is between the first... |
| US-9,825,006 |
Electronic component device and manufacturing method thereof An electronic component device includes a first electronic component, a second electronic component disposed on and connected to the first electronic component,... |
| US-9,825,005 |
Semiconductor package with Pillar-Top-Interconnection (PTI) configuration
and its MIS fabricating method Disclosed is a semiconductor package with Pillar-Top-Interconnection (PTI) configuration, comprising a redistribution layer (RDL) formed on a carrier plane, a... |
| US-9,825,004 |
Semiconductor device A semiconductor device includes a package interface including N numbers of first group of data balls which are disposed on a first side thereof, N numbers of... |
| US-9,825,003 |
Electronic component package and method of manufacturing the same An electronic component package includes a first insulating layer having a via formed therein and a pattern formed thereon, an electronic component disposed on... |
| US-9,825,002 |
Flipped die stack A microelectronic assembly includes a stack of semiconductor chips each having a front surface defining a respective plane of a plurality of planes. A chip... |
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