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Patent # Description
US-9,865,641 Solid-state imaging device, manufacturing method therefor, and imaging apparatus
A solid-state imaging device includes: a first chip including a pixel array in which a plurality of photoelectric conversion portions converting incident light...
US-9,865,640 Backside illuminated (BSI) CMOS image sensor (CIS) with a resonant cavity and a method for manufacturing the...
A backside illuminated semiconductor image sensor that includes a Fabry-Perot resonator tuned to absorb near infrared (NIR) radiation; wherein the Fabry-Perot...
US-9,865,639 Semiconductor device and semiconductor-device manufacturing method
It is possible to reduce resistance variations of a member connecting a through-silicon via to a line and improve wiring reliability. A hole through which the...
US-9,865,638 Semiconductor device and method of manufacturing the same
A semiconductor device includes a first semiconductor substrate having a first wiring layer which includes a first conductive pad, a second semiconductor...
US-9,865,637 Photoelectric conversion device and manufacturing method of the photoelectric conversion device
A manufacturing method includes a first process for forming a first gate electrode for a first MOS transistor and a second gate electrode for a second MOS...
US-9,865,636 Method of simultaneously manufacturing partially shielded pixels
A method of simultaneously manufacturing First and second pixels respectively shielded on a first and on a second side are simultaneously manufactured using a...
US-9,865,635 Image sensor
An image sensor and a method of fabricating the same are disclosed. The image sensor may include a substrate including an active region defined by a device...
US-9,865,634 Image sensor with a reset transistor having spontaneous polarization characteristcs and method for operating...
An image sensor includes a photoelectric conversion element suitable for generating photocharges corresponding to incident light, a transfer transistor suitable...
US-9,865,633 Solid-state imaging device and driving method therefor
A solid-state imaging device in which the potential of a signal line, which is obtained before a pixel has an operating period, is fixed to an intermediate...
US-9,865,632 Image sensor pixel with memory node having buried channel and diode portions formed on N-type substrate
A global shutter image sensor formed on an n-type bulk substrate and including pixels having pinned n-type photodiodes and memory nodes formed in designated...
US-9,865,631 Solid-state image pickup apparatus
Provided is a back-illuminated solid-state image pickup apparatus having an improved color separation characteristic. A photo detector includes a first photo...
US-9,865,630 Image sensor pickup region layout
Embodiments of the present disclosure include an image sensor device and methods of forming the same. An embodiment is an image sensor device including a first...
US-9,865,629 Method of manufacturing array substrate, display substrate, and display device
A method of manufacturing an array substrate, a display substrate and a display device are disclosed. The method of manufacturing an array substrate comprises:...
US-9,865,628 Display device and manufacturing method thereof
The present inventive concept relates to a display device and a manufacturing method thereof. A display device according to an exemplary embodiment of the...
US-9,865,627 Display device and method of manufacturing display device using a mask
Disclosed is a method of manufacturing a display device having a display area and a non-display area, the method including aligning a mask over a substrate, the...
US-9,865,626 Substrate for display device and method of fabricating the same
A method for a display device is discussed. The method according to one embodiment includes forming a substrate of the display device; forming a thin film...
US-9,865,625 Array substrate and method of manufacturing the same, and display device
The present disclosure provides an array substrate and a method of manufacturing the same, and a display device. TA connecting portion is provided within the...
US-9,865,624 Liquid crystal display
A liquid crystal display includes a gate line and a data line disposed on a substrate, a reference voltage line aligned with the data line, and a plurality of...
US-9,865,623 Array substrate and manufacturing method thereof, and display device
An array substrate, a manufacturing method thereof, and a display device are provided. The array substrate includes a peripheral common electrode line for...
US-9,865,622 Array substrate and a method for manufacturing the same
An array substrate is disclosed. The array substrate comprises a base substrate (4) and signal lines on the base substrate (4). The signal lines comprises a...
US-9,865,621 Display device
A display device includes: a pixel electrode; a switching element that is connected to the pixel electrode and charges the pixel electrode; a reference...
US-9,865,620 Semiconductor device having semiconductor layer that includes channel region formed into concave shape,...
A first insulation layer includes a concave portion. A semiconductor layer includes a source area and a drain area, and a channel area disposed at the concave...
US-9,865,619 Array substrate and manufacturing method thereof
An array substrate and a manufacturing method thereof are provided. The method has steps of: forming a buffer layer, a light-shading layer, and a whole...
US-9,865,618 Semiconductor memory device and method for manufacturing same
According to one embodiment, the stacked body includes a plurality of stacked units and a first intermediate layer. Each of the stacked units includes a...
US-9,865,617 Semiconductor device
A semiconductor device includes a first interlayer insulating layer and a second interlayer insulating layer, and a horizontal conductive pattern interposed...
US-9,865,616 Semiconductor memory device and method for manufacturing same
A semiconductor memory device according to one embodiment includes a stacked body, a semiconductor pillar and a plurality of charge storage films. The stacked...
US-9,865,615 Semiconductor device and manufacturing method thereof
A semiconductor device includes bit lines extending along a first direction, the bit lines being arranged along a second direction intersecting the first...
US-9,865,614 Semiconductor device
According to one embodiment, a semiconductor device includes a stacked body and a columnar portion. The stacked body includes a plurality of electrode layers...
US-9,865,613 Semiconductor devices
There is provided a semiconductor device having an arrangement structure in which high-density line patterns having relatively small widths and relatively tight...
US-9,865,612 Semiconductor memory device and method of manufacturing the same
A semiconductr memory device according to an embodiment comprises: a semiconductor substrate; a stacked body having a plurality of first insulating layers and...
US-9,865,611 Multi-tiered semiconductor devices and associated methods
Methods of fabricating multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, a first...
US-9,865,609 One-time-programming (OTP) memory cell with floating gate shielding
A one-time programmable (OTP) memory cell with floating gate shielding is provided. A pair of transistors is arranged on a semiconductor substrate and...
US-9,865,608 Method of forming a device including a floating gate electrode and a layer of ferroelectric material
A method disclosed herein includes providing a semiconductor structure, the semiconductor structure comprising a semiconductor substrate and a gate stack, the...
US-9,865,607 Method of making a fully depleted semiconductor-on-insulator programmable cell and structure thereof
A programmable cell includes a semiconductor-on-insulator substrate, a program gate, and a word line gate. The semiconductor-on-insulator substrate includes a...
US-9,865,606 Semiconductor device and semiconductor memory device
According to one embodiment, a semiconductor device includes a first region having a first conductivity type in a semiconductor region; a second region having a...
US-9,865,605 Memory circuit having resistive device coupled with supply voltage line
A memory circuit includes a first column of memory cells arranged along a first direction, a first supply voltage line extending along the first direction in a...
US-9,865,604 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device having a high degree of freedom of layout has a first part AR1, in which a plurality of p-type wells PW and n-type wells NW are...
US-9,865,603 Transistor structure having N-type and P-type elongated regions intersecting under common gate
A semiconductor structure includes a semiconductor substrate, at least one first elongated region of n-type or p-type, and at least one other second elongated...
US-9,865,602 Semiconductor devices having bit lines and method of fabricating the same
Semiconductor devices and methods of forming the semiconductor devices are provided. The semiconductor devices may include a bit line provided to cross an...
US-9,865,601 Semiconductor integrated circuit
The present disclosure relates to a semiconductor integrated circuit. The semiconductor integrated circuit includes a substrate, a first transistor and a first...
US-9,865,600 Printed capacitors
A device comprises a destination substrate; a multilayer structure on the destination substrate, wherein the multilayer structure comprises a plurality of...
US-9,865,599 Transistor with deep Nwell implanted through the gate
A method of fabricating a CMOS integrated circuit (IC) includes implanting a first n-type dopant at a first masking level that exposes a p-region of a substrate...
US-9,865,598 FinFET with uniform shallow trench isolation recess
Disclosed herein are processes and structures for uniform STI recessing. A method of making a semiconductor device includes initially forming a dense region of...
US-9,865,597 Semiconductor device having fin and dual liner
A semiconductor device is provided as follows. A first fin is formed on a first region of a substrate, extending in a first direction. A second fin is formed on...
US-9,865,596 Low power semiconductor transistor structure and method of fabrication thereof
A structure and method of fabrication thereof relate to a Deeply Depleted Channel (DDC) design, allowing CMOS based devices to have a reduced .sigma.V.sub.T...
US-9,865,595 FinFET device with epitaxial structures that wrap around the fins and the method of fabricating the same
A FinFET device is provided. The FinFET device includes a plurality of fin structures that protrude upwardly out of a dielectric isolation structure. The FinFET...
US-9,865,594 Semiconductor devices
A semiconductor device may include a plurality of wiring structures spaced apart from each other, a protection pattern including a metal nitride on each of the...
US-9,865,593 Semiconductor device and fabrication method thereof
A method for fabricating semiconductor device is disclosed. A substrate having a first transistor on a first region, a second transistor on a second region, a...
US-9,865,592 Method for FinFET integrated with capacitor
A semiconductor structure comprises a semiconductor substrate and a shallow trench isolation (STI) feature over the substrate. The STI feature includes first...
US-9,865,591 Silicon carbide semiconductor device
A silicon carbide semiconductor device includes a transistor region, a diode region, a gate line region, and a gate pad region. The gate pad region and the gate...
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