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Patent # Description
US-9,865,590 Power semiconductor device and method therefor
A power transistor includes a plurality of transistor cells. Each transistor cell has a first electrode coupled to a first electrode interconnection region...
US-9,865,589 System and method of fabricating ESD FinFET with improved metal landing in the drain
A mandrel is formed over an active region that includes a first region and a second region. The first region and the second region are reserved for the...
US-9,865,588 Semiconductor device and electronic device
A semiconductor device that is hardly broken is provided. Alternatively, a semiconductor device having high reliability is provided. The semiconductor device...
US-9,865,587 Method and structure for forming buried ESD with FinFETs
A semiconductor structure is provided that includes an electrostatic discharge (ESD) device integrated on the same semiconductor substrate as semiconductor fin...
US-9,865,586 Semiconductor device and method for testing the semiconductor device
A semiconductor device and a method for testing the semiconductor device are provided. The semiconductor device includes a diode (protection element) and a...
US-9,865,585 LED module and method of manufacturing the same
A compact LED module and a method of manufacturing such an LED module are provided. The LED module includes a first-pole first lead, a first-pole second lead, a...
US-9,865,584 Contact array optimization for ESD devices
A contact array optimization scheme for ESD devices. In one embodiment, contact apertures patterned through a pre-metal dielectric layer over active areas may...
US-9,865,583 Process for making and using a semiconductor wafer containing first and second DOEs of standard cell...
A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOEs), each comprised of at least two fill...
US-9,865,582 Integrated thinfilm resistor and MIM capacitor with a low serial resistance
An electronic device comprising a semiconductor structure having a back end capacitor and a back end thin film resistor and a method of manufacturing the same....
US-9,865,581 Method of fabricating multi-substrate semiconductor devices
A first insulating layer is formed on a substrate. An opening is formed in the first insulating layer. A barrier layer is formed on the first insulating layer...
US-9,865,580 Package on-package with cavity in interposer
A package includes an interposer, which includes a core dielectric material, a through-opening extending from a top surface to a bottom surface of the core...
US-9,865,579 Display device having driver IC directly connected to substrate
In a display device connected with an IC driver, particularly the reliability of connection between an IC terminal located on the outermost side and the IC...
US-9,865,578 Methods of manufacturing multi-die semiconductor device packages and related assemblies
Methods of making semiconductor device packages may involve attaching a first semiconductor die to a carrier wafer, an inactive surface of the first...
US-9,865,577 LED display with wavelength conversion layer
A display and method of manufacture are described. The display may include a substrate including an array of pixels with each pixel including multiple...
US-9,865,576 Solar cell hollow circuit and solar cell display device
A solar cell hollow circuit is provided. The solar cell hollow circuit includes a substrate, a first conductive layer, a photoelectric conversion layer and a...
US-9,865,575 Methods of forming conductive and insulating layers
Methods of forming conductive and insulating layers for semiconductor devices and packages. Substrate is provided with integrated circuit device and...
US-9,865,574 Alignment in the packaging of integrated circuits
A method includes aligning a top package to a bottom package using an alignment mark in the bottom package, and placing the top package over the bottom package,...
US-9,865,573 Light emitting device
A light emitting device including a supporting body; first wirings formed on a surface of the supporting body; second wirings formed on the surface of the...
US-9,865,572 Display device using semiconductor light emitting device and method for manufacturing
A display device including a substrate including a wiring electrode; a conductive adhesive layer including an anisotropic conductive medium, and disposed to...
US-9,865,571 Light emitting diode lighting module
A light emitting diode (LED) lighting module includes a plurality of LED components and a carrier. The LED components are electrically connected in series, and...
US-9,865,570 Integrated circuit package with thermally conductive pillar
Embodiments of the present disclosure relate to an integrated circuit (IC) package, including a molding compound positioned on a first die and laterally...
US-9,865,569 Planarity-tolerant reworkable interconnect with integrated testing
A structure includes an electrical interconnection between a first substrate including a plurality of protrusions and a second substrate including a plurality...
US-9,865,568 Integrated circuit structures with recessed conductive contacts for package on package
Disclosed herein are integrated circuit (IC) structures having recessed conductive contacts for package on package (PoP). For example, an IC structure may...
US-9,865,567 Heterogeneous integration of integrated circuit device and companion device
An example method of manufacturing a semiconductor assembly includes: forming first integrated circuit (IC) dies and dummy dies; forming an interposer wafer...
US-9,865,566 Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a substrate, a redistribution layer (RDL) including a dielectric layer disposed over the substrate and a plurality of...
US-9,865,565 Transient interface gradient bonding for metal bonds
A method and apparatus for performing metal-to-metal bonding for an electrical device and an electrical device produced thereby. For example and without...
US-9,865,564 Laser ashing of polyimide for semiconductor manufacturing
A system for laser ashing of polyimide for a semiconductor manufacturing process is provided. The system includes: a semiconductor chip, a top chip attached to...
US-9,865,563 Wire tensioner
A wire tensioner has a wire passage through which a wire is inserted. The wire passage include: an inlet through which a compressed gas enters; a first outlet...
US-9,865,562 Bonding device
To provide a bonding device capable of adequately controlling a leading end of a capillary when a ball formed at a leading end of a wire is pressed and bonded...
US-9,865,561 Electronic package having a supporting board and package carrier thereof
A package carrier is provided. The package carrier includes a wiring layer and an insulating pattern. The wiring layer includes at least one connecting pad and...
US-9,865,560 Methods of forming wire interconnect structures
A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding tool;...
US-9,865,559 Method for manufacturing stretchable wire and method for manufacturing stretchable integrated circuit
Provided is a method for manufacturing a stretchable wire, the method including removing a portion of a photoresist layer on a substrate to form a photoresist...
US-9,865,558 Semiconductor device connected by anisotropic conductive film
A semiconductor device connected by an anisotropic conductive film, the anisotropic conductive film having a differential scanning calorimeter onset temperature...
US-9,865,557 Reduction of solder interconnect stress
An electrical contact upon an interposer and/or upon a processing device includes a minor axis and a major axis. The contact is positioned such that the major...
US-9,865,556 Semiconductor device and method of self-confinement of conductive bump material during reflow without solder mask
A semiconductor device has a semiconductor die with a die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is...
US-9,865,555 Self-aligned under bump metal
An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with...
US-9,865,554 Integrated circuit packaging system with under bump metallization and method of manufacture thereof
An integrated circuit packaging system and method of manufacture thereof including: providing a substrate; forming contact pads on top of the substrate; forming...
US-9,865,553 Microelectronics package with inductive element and magnetically enhanced mold compound component
The present disclosure relates to a microelectronics package with an inductive element and a magnetically enhanced mold compound component, and a process for...
US-9,865,552 Wafer level package
A water level package includes a substrate, a plurality of semiconductor chips mounted on the substrate, and molding members that contact the substrate and the...
US-9,865,551 Methods to control wafer warpage upon compression molding thereof and articles useful therefor
Provided herein are multilayer structures having a reduced propensity to warp upon curing of certain components thereof. In one aspect, there are provided...
US-9,865,550 Pattern generator having stacked chips
A pattern generator includes and upper chip and one or more lower chips. The upper chip includes an upper substrate and a plurality of conductive plates on the...
US-9,865,549 Semiconductor device, manufacturing method thereof, and electronic apparatus
A semiconductor device includes a wiring layer that includes at least one low-dielectric rate interlayer insulating film layer; a guard ring that is formed by...
US-9,865,548 Polymer member based interconnect
An interconnect (124) suitable for attachment of integrated circuit assemblies to each other comprises a polymer member (130) which is conductive and/or is...
US-9,865,547 Semiconductor device and manufacturing method thereof
According to one embodiment, a semiconductor device is disclosed. The device includes a graphene layer containing impurities, and including a first region and a...
US-9,865,546 Contacts to semiconductor substrate and methods of forming same
An aspect of the invention includes a method for forming a contact in a dielectric layer over a semiconductor substrate. The method may comprise: forming a...
US-9,865,545 Plurality of substrates bonded by direct bonding of copper recesses
A structure includes a substrate having an upper surface provided with recesses and coated with a continuous barrier layer topped with a continuous copper layer...
US-9,865,544 Semiconductor device layout having a power rail
A semiconductor device is provided as follows. An active region extends along a first direction. A gate line overlaps the active region and extending along a...
US-9,865,543 Structure and method for inhibiting cobalt diffusion
A process for forming a conductive structure includes the formation of a self-aligned, inlaid conductive cap over a cobalt-based contact. The inlaid conductive...
US-9,865,542 Interconnect structure with misaligned metal lines coupled using different interconnect layer
In some embodiments, an interconnect structure includes first and second metal lines, and an end-to-end portion. The first metal line is formed in a first...
US-9,865,541 Memory device having cell over periphery structure and memory package including the same
A memory device includes a substrate, and a peripheral circuit disposed on a first surface of the substrate. The peripheral circuit includes a first transistor....
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