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Patent # Description
US-9,865,540 Vertical memory devices and methods of manufacturing the same
A vertical memory device includes a plurality of gate lines, at least one etch-stop layer, channels, and contacts. The gate lines are stacked and spaced apart...
US-9,865,539 Structure and formation method of semiconductor device structure
Structures and formation methods of a semiconductor device structure are provided. The method includes forming a dielectric layer over a semiconductor...
US-9,865,538 Metallic blocking layer for reliable interconnects and contacts
A semiconductor structure is provided that includes a first interconnect dielectric layer containing a first interconnect metal structure embedded therein. A...
US-9,865,537 Methods and apparatus for integrated circuit failsafe fuse package with arc arrest
In described examples, an apparatus includes: an integrated circuit die having multiple terminals; the integrated circuit die positioned on a die pad portion of...
US-9,865,536 Electrical fuse structure and method of formation
An embodiment is a fuse structure. In accordance with an embodiment, a fuse structure comprises an anode, a cathode, a fuse link interposed between the anode...
US-9,865,535 Semiconductor device
A semiconductor device includes a planar interconnection layer formed on a substrate and made of a semiconductor, a first pillar-shaped semiconductor layer...
US-9,865,534 Stress reduction apparatus
A device comprises a metal via having a lower portion in a first etch stop layer and an upper portion in a first dielectric layer over a substrate, a second...
US-9,865,533 Feedthrough assemblies
Various embodiments of a feedthrough assembly and methods of forming such assemblies are disclosed. In one or more embodiments, the feedthrough assembly can...
US-9,865,532 Molded body and electrical device having a molded body for high voltage applications
An electrical device comprising a ribbed molded body housing an electrical component is provided. The ribbed molded body includes at least one surface or...
US-9,865,531 Power module package having patterned insulation metal substrate
A power module package is provided, including a substrate, a first chip, and a second chip. The substrate includes a metal carrier, a patterned insulation layer...
US-9,865,530 Assembly comprising an element that is capable of transmitting heat, a film of a polymer that is a good thermal...
An assembly comprises: at least one element that is capable of transmitting heat; at least one electrically insulating substrate comprising at least one film of...
US-9,865,529 Semiconductor module with conductive pin
A semiconductor module including a circuit block that has an electrically insulating layer, a plurality of circuit patterns formed on one surface of the...
US-9,865,528 High power and high frequency plastic pre-molded cavity package
A cavity package is set forth along with a method of manufacturing thereof. According to one embodiment, the method comprises attaching a metal heat sink to a...
US-9,865,527 Packaged semiconductor device having nanoparticle adhesion layer patterned into zones of electrical conductance...
A device comprises a substrate and an adhesive nanoparticle layer patterned into zones of electrical conductance and insulation on top of the substrate surface....
US-9,865,526 Chip package and method for forming the same
A chip package including a first substrate having an upper surface, a lower surface and a sidewall is provided. A sensing region or device region and a...
US-9,865,525 Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units
A semiconductor device has a carrier with a die attach area. A semiconductor die is mounted to the die attach area with a back surface opposite the carrier. A...
US-9,865,524 Semiconductor device and method of forming conductive vias using backside via reveal and selective passivation
A semiconductor device includes a plurality of semiconductor die and a plurality of conductive vias formed in the semiconductor die. An insulating layer is...
US-9,865,523 Robust through-silicon-via structure
Methods and apparatus entailing an interconnect structure comprising interconnect features disposed in dielectric material over a substrate. Each interconnect...
US-9,865,522 Composite heat sink structures
Composite heat sink structures and methods of fabrication are provided, with the composite heat sink structures including: a thermally conductive base having a...
US-9,865,521 Copper nanorod-based thermal interface material (TIM)
A copper nanorod thermal interface material (TIM) is described. The copper nanorod TIM includes a plurality of copper nanorods having a first end thermally...
US-9,865,520 Tunable semiconductor band gap reduction by strained sidewall passivation
A semiconductor device includes a mesa structure having vertical sidewalls, the mesa structure including an active area comprising a portion of its height. A...
US-9,865,519 Use of an external getter to reduce package pressure
A system and method for forming a wafer level package. In one example, a substrate used in the wafer level package includes a surface defined by a wafer level...
US-9,865,518 Electromagnetic wave shielding support base-attached encapsulant, encapsulated substrate having semicondutor...
The present invention provides an electromagnetic wave shielding support base-attached encapsulant for collectively encapsulating a semiconductor device...
US-9,865,516 Wafers having a die region and a scribe-line region adjacent to the die region
A wafer and a forming method thereof are provided. The wafer has a die region and a scribe-line region adjacent to the die region, and includes a conductive...
US-9,865,515 Ion implantation methods and structures thereof
A semiconductor device fabricated using a high-temperature ion implantation process is provided. The high-temperature ion implantation process includes...
US-9,865,514 Inline measurement of through-silicon via depth
A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure...
US-9,865,513 Semiconductor device manufacturing method
A semiconductor device manufacturing method includes an element forming step of forming an element structure on a front surface of a substrate and forming a...
US-9,865,512 Dynamic design attributes for wafer inspection
Methods and systems for dynamic design attributes for wafer inspection are provided. One method includes, at run time of a wafer inspection recipe, prompting a...
US-9,865,511 Formation of strained fins in a finFET device
In an aspect of the present invention, a field-effect transistor (FET) structure is formed. The FET structure comprises a plurality of fins formed on a...
US-9,865,510 Device and methods for high-K and metal gate slacks
A semiconductor device having five gate stacks on different regions of a substrate and methods of making the same are described. The device includes a...
US-9,865,509 FinFET CMOS with Si NFET and SiGe PFET
A method for forming a complementary metal oxide semiconductor (CMOS) device includes growing a SiGe layer on a Si semiconductor layer, and etching fins through...
US-9,865,508 Method and structure to fabricate closely packed hybrid nanowires at scaled pitch
Techniques for forming closely packed hybrid nanowires are provided. In one aspect, a method for forming hybrid nanowires includes: forming alternating layers...
US-9,865,507 Low-cost CMOS structure with dual gate dielectrics and method of forming the CMOS structure
Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of...
US-9,865,506 Stack type semiconductor memory device
A stack type memory device and a method of manufacturing the same are provided. The stack type memory device includes a semiconductor substrate, a plurality of...
US-9,865,505 Method for reducing N-type FinFET source and drain resistance
A method of manufacturing a semiconductor device includes providing a substrate structure, the substrate structure having a semiconductor substrate including a...
US-9,865,504 Semiconductor device and manufacturing method thereof
A semiconductor device includes an isolation layer disposed over a substrate, first and second fin structures, a gate structure, a source/drain structure and a...
US-9,865,503 Method to produce a semiconductor wafer for versatile products
Aspects of the disclosure provide a method for semiconductor wafer manufacturing. The method includes utilizing a subset of lower level masks in a mask set to...
US-9,865,502 Semiconductor device and method of manufacturing the same semiconductor device
The semiconductor device includes a semiconductor layer in which a via hole penetrating an upper surface of the semiconductor layer to a lower surface of the...
US-9,865,501 Method and apparatus for remote plasma treatment for reducing metal oxides on a metal seed layer
Method and apparatus for reducing metal oxide surfaces to modified metal surfaces are disclosed. By exposing a metal oxide surface to a remote plasma, the metal...
US-9,865,500 Method of fine line space resolution lithography for integrated circuit features using double patterning technology
A method includes forming a hard mask over a base material, and forming an I-shaped first opening in the hard mask. The first opening includes two parallel...
US-9,865,499 Method and apparatus for gap fill using deposition and etch processes
A method for depositing a silicon-containing film is performed by causing a silicon-containing gas to adsorb on a first surface of a depression formed in a...
US-9,865,498 Isolated semiconductor layer over buried isolation layer
An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of...
US-9,865,497 Method for manufacturing bonded wafer
A method for manufacturing bonded wafer including: producing bonded wafer having thin-film on its base wafer by an ion implantation delamination method, and...
US-9,865,496 Method for manufacturing isolation structure
A method for manufacturing a semiconductor device includes forming a first trench and a second trench in a substrate, the first and the second trenches...
US-9,865,495 Semiconductor device and method for fabricating the same
A method of fabricating a semiconductor device includes forming a plurality of mask patterns comprising a real mask pattern and a dummy mask pattern on a...
US-9,865,494 Substrate holding method, substrate holding apparatus, exposure apparatus and exposure method
A wafer holding apparatus for holding a wafer including a wafer holder on which the wafer is placed; and a lift pin that is configured to be lifted up and down...
US-9,865,493 Substrate plating jig
A plating jig that can form a metal plating film simultaneously on both surfaces of a semiconductor wafer by one plating process. The plating jig includes a...
US-9,865,492 Receiving device for handling structured substrates
A mounting apparatus for handling of a structured substrate which has structures. The mounting apparatus having a soft material layer for accommodating the...
US-9,865,491 Devices for methodologies related to wafer carriers
Disclosed are systems, devices and methodologies for handling wafers in wafer processing operations through use of wafer carriers. In an example situation, a...
US-9,865,490 Cyclic olefin polymer compositions and polysiloxane release layers for use in temporary wafer bonding processes
The invention broadly relates to cyclic olefin polymer bonding compositions and release compositions, to be used independently or together, that enable thin...
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