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Patent # Description
US-9,864,727 Providing dynamically scaling computing load balancing
Techniques are described for providing load balancing functionality among multiple computing nodes. In some situations, the provided load balancing ...
US-9,864,726 Information processing apparatus, information processing method, and non-transitory computer-readable medium
An information processing apparatus includes a determination unit, a first acceptance unit, a second acceptance unit, a measurement unit, a third acceptance...
US-9,864,725 Managing use of program execution capacity
Techniques are described for managing execution of programs. In some situations, program execution is managed for multiple users using excess program execution...
US-9,864,724 Method and device for serial data transmission having a flexible message size and a variable bit length
A method for serial data transfer in a bus system having at least two bus subscribers that exchange messages via the bus, the transmitted messages having a CAN...
US-9,864,723 Information-processing apparatus, information-processing method, and program
An information-processing method performed in an information-processing apparatus, the information-processing apparatus performing wireless communication with a...
US-9,864,722 System and method for communication between a data-acquisition circuit and a data-processing circuit
A communication system coupled to a data-acquisition circuit and to a data-processing circuit is provided, including at least one shift register, an addressing...
US-9,864,721 Cascaded fieldbus system
For simplified projection of a cascaded fieldbus system which includes a first fieldbus with a plurality of first bus devices, a second fieldbus subordinate to...
US-9,864,720 Data processing circuit for controlling sampling point independently and data processing system including the same
A data processing circuit includes a delay circuit configured to delay a data signal and generate delayed data signals each having a different delay; and an...
US-9,864,719 Systems and methods for power optimization at input/output nodes of an information handling system
In accordance with methods of the present disclosure, a system may include a switch and a management controller communicatively coupled to the switch. The...
US-9,864,718 Physical layer network interface module (PHY-NIM) adaptation system
A physical layer network interface module (PHY-NIM) adaptation system provides a PHY-NIM device and an attachable media access control (MAC) device. The PHY-NIM...
US-9,864,717 Input/output processing
The present disclosure provides an electronic device that includes a lower device configured to process local input/output communications between the electronic...
US-9,864,716 Receiving buffer credits by a plurality of channels of one or more host computational devices for transmitting...
A channel of a host computational device sends a command to transfer data to a control unit included in a storage controller. The channel of the host...
US-9,864,715 Bus system using plurality of non-overlapping frequency bands for communication
The invention relates to a bus system for transmitting data between data processing units in a network, by means of a bus that consists of two signal lines. The...
US-9,864,714 Electronic system for performing recharging and data communication
An electric system includes a transmission line, a first and a second electronic devices, wherein the second electronic device selectively electrically connects...
US-9,864,713 Optimal sampling of data-bus signals using configurable individual time delays
A method includes receiving a group of logic signals to be sampled at a common sampling timing. Individual time delays, which individually align each of the...
US-9,864,712 Shared receive queue allocation for network on a chip communication
A method for communicating data in a processing architecture comprising a plurality of interconnected IP blocks. Transmitting IP blocks may transmit messages to...
US-9,864,711 Automatic downstream to upstream mode switching at a universal serial bus physical layer
Examples are disclosed for automatic downstream to upstream mode switching at a universal serial bus (USB) physical (PHY) layer including activating a switching...
US-9,864,710 Writing data to storage via a PCI express fabric having a fully-connected mesh topology
A method for writing data to a persistent storage module ("PSM") in a communication fabric is discussed. A write request is received from a processor at a PSM....
US-9,864,709 Data transfer in a multi-core processor
Techniques described herein are generally related to data transfer in multi-core processor devices. A core of a multi-core processor device may be configured to...
US-9,864,708 Safely discovering secure monitors and hypervisor implementations in systems operable at multiple hierarchical...
In a computer system operable at multiple hierarchical privilege levels, a "wait-for-event" (WFE) communication channel between components operating at...
US-9,864,707 Time multiplexing at different rates to access different memory types
A memory controller accesses different types of memory devices running at different native rates through the use of a time division multiplexed bus. Data is...
US-9,864,706 Management of allocation for alias devices
Embodiments of the present invention provide systems, methods, and computer program products for managing computing devices to handle an input/output (I/O)...
US-9,864,705 Dynamic access method switching for open data sets
A method for switching between access methods while a data set is open includes attempting, on behalf of a first system, to gain access to a data set. The...
US-9,864,704 Memory controller communicating with host, operating method thereof, and computing system including the same
A semiconductor device includes a nonvolatile memory storing encrypted management data, and a memory controller coupled between the nonvolatile memory and a...
US-9,864,703 Cache memory having enhanced performance and security features
A cache memory having enhanced performance and security feature is provided. The cache memory includes a data array storing a plurality of data elements, a tag...
US-9,864,702 Techniques to prelink software to improve memory de-duplication in a virtual system
Techniques to prelink software to improve memory de-duplication in a virtual system are described. An apparatus may comprise a processor circuit, a memory unit...
US-9,864,701 Resource mapping for an input/output device
One or more resources for an SoC can be directly mapped to a host address space in a host system as peripheral bus functions. A translation unit can provide...
US-9,864,700 Method and apparatus for power reduction in a multi-threaded mode
A method and apparatus for reducing dynamic power consumption in a multi-thread content-addressable memory is described. The apparatus includes a first input...
US-9,864,699 Method and apparatus for compressing LUT
Aspects of the disclosure provide a circuit that includes a memory circuit and a controller circuit. The memory circuit is to have a look-up table (LUT) that...
US-9,864,698 Resolving cache lookup of large pages with variable granularity
A method, system, and computer program product for resolving cache lookup of large pages with variable granularity are provided in the illustrative embodiments....
US-9,864,697 Memory having a static cache and a dynamic cache
The present disclosure includes memory having a static cache and a dynamic cache. A number of embodiments include a memory, wherein the memory includes a first...
US-9,864,696 Multilevel cache-based data read/write method and apparatus, and computer system
A multilevel cache-based data read/write method and a computer system. The method includes acquiring a query address of a physical memory data block in which...
US-9,864,695 Implementing hardware accelerator for storage write cache management for managing cache destage rates and...
A method and controller for implementing storage adapter enhanced write cache management, and a design structure on which the subject controller circuit resides...
US-9,864,694 Tracking the content of a cache using a way tracker having entries with a cache miss indicator
A cache is provided comprising a plurality of ways, each way of the plurality of ways comprising a data array, wherein a data item stored by the cache is stored...
US-9,864,693 Data processing method, information processing device, and recording medium
A data processing method executed by a processor included in an information processing device, the data processing method includes reserving a storage area of a...
US-9,864,692 Managing read tags in a transactional memory
Managing cache evictions during transactional execution of a process. Based on initiating transactional execution of a memory data accessing instruction, memory...
US-9,864,691 Deletion indication implementation based on internal model
The subject disclosure is generally directed towards caching property values in a sparse cache for use in translating notifications to contain property values...
US-9,864,690 Detecting cache conflicts by utilizing logical address comparisons in a transactional memory
A processor in a multi-processor configuration is configured perform dynamic address translation from logical addresses to real address and to detect memory...
US-9,864,689 Near cache distribution in in-memory data grid (IMDG) non structured query language (NO-SQL) environments
Near cache distribution in in-memory data grid environment that utilizes manifest of keys may be provided. An application instance may be initialized that...
US-9,864,688 Discarding cached data before cache flush
Described are techniques for processing data. A notification is sent from an application to a cache manager to invalidate any cache location storing data for a...
US-9,864,687 Cache coherent system including master-side filter and data processing system including same
An application processor is provided. The application processor includes a cache coherent interconnect, a first master device connected to the cache coherent...
US-9,864,686 Restriction of validation to active tracks in non-volatile storage during a warmstart recovery
A storage system, maintains a cache and a non-volatile storage. Active tracks in the non-volatile storage are determined. The determined active tracks in the...
US-9,864,685 Method and system for cache tiering
A method and system for storing data for retrieval by an application running on a computer system including providing a tiered caching system including at least...
US-9,864,684 Performing efficient cache invalidation
Performing efficient cache invalidation is disclosed, including: receiving an invalidation request to invalidate one or more invalidated cache entries at a...
US-9,864,683 Managing cache for improved data availability by associating cache pages with respective data objects
A technique for managing a cache in a data storage system includes creating metadata that associates cache pages with respective data objects and storing the...
US-9,864,682 Nonvolatile memory device and storage device having the same and operation method thereof
According to example embodiments, a method of operating a storage device includes reading a process capability index using a memory controller, adjusting at...
US-9,864,681 Dynamic multithreaded cache allocation
Apparatus and method embodiments for dynamically allocating cache space in a multi-threaded execution environment are disclosed. In some embodiments, a...
US-9,864,680 Virtual storage address threshold for freemained frames
Address-based thresholds for freemained frames are used to determine retention actions. Based, at least in part, on a comparison of a number of freemained...
US-9,864,679 Identifying severity of test execution failures by analyzing test execution logs
The method includes identifying a test report log for a regression test. The method further includes identifying one or more errors in the identified test...
US-9,864,678 Automatic risk analysis of software
Techniques are described herein that are capable of performing automatic risk analysis of software. An automatic risk analyzer may determine correlations...
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