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Patent # Description
US-9,893,193 Thin-film transistor including a gate electrode with a side wall insulating layer and display device
A method of fabricating a thin-film transistor includes: forming an oxide semiconductor layer above a substrate; forming a gate insulating layer above the oxide...
US-9,893,192 Semiconductor device
To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device formed...
US-9,893,191 FinFET transistor with u-shaped channel
A semiconductor device having a u-shaped FinFET and methods of forming the same are disclosed. The semiconductor device includes a substrate and a fin over the...
US-9,893,190 Fin FET and method of fabricating same
A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by...
US-9,893,189 Method for reducing contact resistance in semiconductor structures
Semiconductor structures and methods reduce contact resistance, while retaining cost effectiveness for integration into the process flow by introducing a...
US-9,893,188 Semiconductor structure with template for transition metal dichalcogenides channel material growth
A semiconductor structure includes a substrate, a buffer layer, and a two-dimensional layered material. The buffer layer is above the substrate and is formed...
US-9,893,187 Sacrificial non-epitaxial gate stressors
A method for fabricating a fin field effect transistor (finFET) device with a strained channel. During fabrication, after the fin is formed, a dummy gate is...
US-9,893,186 Methods of fabricating semiconductor devices
Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active...
US-9,893,185 Fin field effect transistor and method for fabricating the same
A FinFET including a substrate, a plurality of isolation structures, a plurality of blocking layers, and a gate stack is provided. The substrate has a plurality...
US-9,893,184 Fin-type field effect transistor device and method of fabricating the same
In accordance with some embodiments of the present disclosure, a fin-FET device includes a substrate, a stack structure, a source and drain region, a sidewall...
US-9,893,183 Semiconductor structure and manufacturing method thereof
Some embodiments of the present disclosure provide a semiconductor structure including a substrate and an epitaxy region partially disposed in the substrate....
US-9,893,182 FinFET and method for forming the same
The present disclosure provides a method for forming a field-effect fin transistor (FinFET) structure. The method includes providing a substrate with fin...
US-9,893,181 Uniform gate length in vertical field effect transistors
A method of fabricating a vertical field effect transistor includes forming a base layer on a doped layer that is formed on a substrate, and forming fin hard...
US-9,893,180 Semiconductor device
A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a...
US-9,893,179 Method for producing semiconductor device and semiconductor device
A method for producing a semiconductor device includes a first step of forming a first insulating film around a fin-shaped semiconductor layer on a...
US-9,893,178 Semiconductor device having a channel separation trench
A semiconductor device includes a transistor formed in a semiconductor substrate having a main surface. The transistor includes a source region of a first...
US-9,893,177 Silicon carbide semiconductor device and method of manufacturing the same
A silicon carbide semiconductor device includes a silicon carbide semiconductor layer having a main surface, the main surface of the silicon carbide...
US-9,893,176 Silicon-carbide trench gate MOSFETs
In a general aspect, an apparatus can include a silicon carbide (SiC) trench gate MOSFET with improved operation due, at least in part, to a reduced gate...
US-9,893,175 Integrated circuit with a power transistor and a driver circuit integrated in a common semiconductor body
An integrated circuit includes a power transistor and a drive circuit. The drive circuit includes at least one drive transistor. The power transistor and the at...
US-9,893,174 III-nitride based N polar vertical tunnel transistor
A semiconductor structure, device, or N-polar III-nitride vertical field effect transistor. The structure, device, or transistor includes a current blocking...
US-9,893,173 Method for fabricating a metallic oxide thin film transistor
A method for fabricating a metal oxide thin film transistor comprises the steps of: selecting a substrate and fabricating a gate electrode on the substrate;...
US-9,893,172 Methods to integrate SONOS into CMOS flow
A method of forming a transistor is described. In one embodiment the method includes: forming a channel of a transistor in a surface of a substrate; forming a...
US-9,893,171 Fin field effect transistor fabrication and devices having inverted T-shaped gate
A method of forming a fin field effect transistor (finFET), including forming a temporary gate structure having a sacrificial gate layer and a dummy gate layer...
US-9,893,170 Manufacturing method of selectively etched DMOS body pickup
A method for fabricating a LDMOS device in a well region of a semiconductor substrate, including: forming a body region and a source layer in the well region...
US-9,893,169 Fabrication of a vertical fin field effect transistor having a consistent channel width
A method of forming a vertical fin field effect transistor having a consistent channel width, including forming one or more vertical fin(s) on the substrate,...
US-9,893,168 Split gate semiconductor device with curved gate oxide profile
A split gate semiconductor device includes a trench gate having a first electrode region and a second electrode region that are separated from each other by a...
US-9,893,167 Integration methods to fabricate internal spacers for nanowire devices
A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device...
US-9,893,166 Dummy gate formation using spacer pull down hardmask
Forming a dummy gate on a semiconductor device is disclosed. A first sacrificial layer is formed on a fin, and a second sacrificial layer is formed on the first...
US-9,893,165 Method for manufacturing array substrate and manufacturing device
Embodiments of the present invention disclose a manufacturing method for an array substrate and corresponding manufacturing device, which belong to the...
US-9,893,164 Bipolar transistor device fabrication methods
A method of fabricating a bipolar transistor device includes performing a first plurality of implantation procedures to implant dopant of a first conductivity...
US-9,893,163 3D capacitor and method of manufacturing same
A 3D capacitor and method for fabricating a 3D capacitor is disclosed. An exemplary 3D capacitor includes a substrate including a fin structure, the fin...
US-9,893,162 Silicon carbide semiconductor device and method of manufacturing silicon carbide semiconductor device
Heat treatment is performed twice with respect to a silicon carbide substrate. In the first heat treatment process, after Si ions are implanted in a front...
US-9,893,161 Parasitic capacitance reduction structure for nanowire transistors and method of manufacturing
Embodiments of the invention describe parasitic capacitance reduction structure for nanowire transistors and method of manufacturing. According to one...
US-9,893,160 Methods of forming gate dielectric material
A method of fabricating a semiconductor device includes contacting water with a silicon oxide layer. The method further includes diffusing an ozone-containing...
US-9,893,159 Transistor, integrated circuit and method of fabricating the same
A transistor, an integrated circuit and a method of fabricating the integrated circuit are provided. In various embodiments, the transistor includes a source...
US-9,893,158 Semiconductor device comprising a gradually increasing field dielectric layer and method of manufacturing a...
A semiconductor device is provided that includes a transistor in a semiconductor body having a main surface. The transistor includes a source region, a drain...
US-9,893,157 Structures with contact trenches and isolation trenches
Structures that include contact trenches and isolation trenches, as well as methods for forming structures including contact trenches and isolation trenches. A...
US-9,893,156 Segmented field plate structure
A device includes a transistor formed over a substrate. The transistor includes a source structure, a drain structure, and a gate structure. A dielectric layer...
US-9,893,155 Semiconductor electronic device formed of 2-D van der Waals material whose free charge carrier concentration is...
Embodiments of the present invention are directed to semiconductor electronic devices formed of 2-D van der Waals material whose free charge carrier...
US-9,893,154 Recess liner for silicon germanium fin formation
Semiconductor device fabrication method and structures are provided having a substrate structure which includes a silicon layer at an upper portion. The silicon...
US-9,893,153 Semiconductor device and method of manufacturing the same
A semiconductor device according to an embodiment includes a SiC layer, a gate electrode, a gate insulating film provided between the SiC layer and the gate...
US-9,893,152 Semi-insulating silicon carbide monocrystal and method of growing the same
A semi-insulating silicon carbide monocrystal and a method of growing the same are disclosed. The semi-insulating silicon carbide monocrystal comprises...
US-9,893,151 Method and apparatus providing improved thermal conductivity of strain relaxed buffer
A structure includes a substrate and a strain relaxed buffer (SRB) that has a bottom surface disposed on the substrate and an opposite top surface. The SRB is...
US-9,893,150 Structure and method for semiconductor device
A semiconductor device and a method of forming the same are disclosed. The semiconductor device includes a substrate, and a source region and a drain region...
US-9,893,149 High mobility strained channels for fin-based transistors
Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein...
US-9,893,148 Method for fabricating a transistor device with a tuned dopant profile
A transistor device with a tuned dopant profile is fabricated by implanting one or more dopant migrating mitigating material such as carbon. The process...
US-9,893,147 Fully substrate-isolated FinFET transistor
Channel-to-substrate leakage in a FinFET device is prevented by inserting an insulating layer between the semiconducting channel and the substrate during...
US-9,893,146 Lateral DMOS and the method for forming thereof
A lateral DMOS device with peak electric field moved below a top surface of the device along a body-drain junction is introduced. The LDMOS has a deep body and...
US-9,893,145 On chip MIM capacitor
On-chip, three-dimensional MIM capacitors are provided. In one aspect, a method for forming a device includes: forming at least one MOSFET structure and at...
US-9,893,144 Methods for fabricating metal-insulator-metal capacitors
Semiconductor devices having MIM capacitor structures are provided, as well as methods for fabricating semiconductor devices having MIM capacitor structures....
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