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Patent # Description
US-9,911,873 Hydrogenation of passivated contacts
Methods of hydrogenation of passivated contacts using materials having hydrogen impurities are provided. An example method includes applying, to a passivated...
US-9,911,872 Composition for forming electrode of solar cell, and electrode manufactured using same
A composition for solar cell electrodes and electrodes fabricated using the same. The composition includes a silver (Ag) powder; a glass frit containing about...
US-9,911,871 Reflective photovoltaics
A photovoltaic module includes colorized reflective photovoltaic cells that act as pixels. The colorized reflective photovoltaic cells are arranged so that...
US-9,911,870 Solid-state imaging element, method for manufacturing solid-state imaging element, and electronic device
A solid-state imaging element including: a sensor substrate in which a photoelectric conversion section is arranged and formed; a circuit substrate in which a...
US-9,911,869 Diode with reduced recovery time for applications subject to the current recirculation phenomenon and/or to...
A diode comprising a semiconductor body delimited by a front surface and including: a first semiconductor region having a first type of conductivity, facing at...
US-9,911,868 Nitride semiconductor device
A nitride semiconductor device includes: a conductive substrate; a first nitride semiconductor layer which is formed on the substrate and contains Ga or Al; an...
US-9,911,867 Fin-based nonvolatile memory structures, integrated circuits with such structures, and methods for fabricating same
Integrated circuits, nonvolatile memory (NVM) structures, and methods for fabricating integrated circuits with NVM structures are provided. An exemplary...
US-9,911,866 Field effect transistor
An insulating film is provided over one surface of a first semiconductor layer including a first oxide semiconductor including indium as a main component, and a...
US-9,911,865 Semiconductor device and method for manufacturing the semiconductor device
An object is to provide favorable interface characteristics of a thin film transistor including an oxide semiconductor layer without mixing of an impurity such...
US-9,911,864 Semiconductor device
Defects in an oxide semiconductor film are reduced in a semiconductor device including the oxide semiconductor film. The electrical characteristics of a...
US-9,911,863 Thin film transistor and manufacturing method of thin film transistor
According to one embodiment, a manufacturing method of thin film transistor includes forming an oxide semiconductor layer on a first insulating film, forming a...
US-9,911,861 Semiconductor device, manufacturing method of the same, and electronic device
A semiconductor device in which parasitic capacitance is reduced is provided. A first insulating layer is deposited over a substrate. A first oxide insulating...
US-9,911,860 Semiconductor device and method for manufacturing the same
An object is to improve field effect mobility of a thin film transistor using an oxide semiconductor. Another object is to suppress increase in off current even...
US-9,911,859 Thin-film transistor and method of manufacturing the same field
According to one embodiment, a thin-film transistor and a method of manufacturing the same achieve size reduction of the thin-film transistor while using an...
US-9,911,858 Semiconductor device and method for manufacturing the same
A miniaturized semiconductor device including a transistor in which a channel formation region is formed using an oxide semiconductor film and variation in...
US-9,911,857 Thin film transistor with low trap-density material abutting a metal oxide active layer and the gate dielectric
A metal oxide semiconductor device including an active layer of metal oxide, a layer of gate dielectric, and a layer of low trap density material. The layer of...
US-9,911,856 Semiconductor device
One of objects is to provide a semiconductor device with stable electric characteristics, in which an oxide semiconductor is used. The semiconductor device...
US-9,911,855 Top metal pads as local interconnectors of vertical transistors
An integrated circuit structure includes a first vertical transistor and a second vertical transistor. The first vertical transistor includes a first...
US-9,911,854 Source/drain conductors for transistor devices
A transistor device comprising: source and drain conductors connected by a semiconductor channel provided by a layer of semiconductor material formed over the...
US-9,911,853 Semiconductor device
In a semiconductor device using a transistor including an oxide semiconductor, a change in electrical characteristics is suppressed and reliability is improved....
US-9,911,852 Gate-all-around fin device
A gate-all around fin double diffused metal oxide semiconductor (DMOS) devices and methods of manufacture are disclosed. The method includes forming a plurality...
US-9,911,851 Integrated circuit devices having air-gap spacers above gate electrodes
Integrated circuit devices having a cavity and methods of manufacturing the integrated circuit devices are provided. The integrated circuit devices may include...
US-9,911,850 FinFETs and the methods for forming the same
A method includes providing a plurality of semiconductor fins parallel to each other, and includes two edge fins and a center fin between the two edge fins. A...
US-9,911,849 Transistor and method of forming same
A first aspect of the invention provides for a transistor. The transistor may include a gate stack on a substrate; a channel under the gate stack within the...
US-9,911,848 Vertical transistor and method of manufacturing the same
A vertical transistor includes a source-channel-drain structure, a gate and a gate dielectric layer. The source-channel-drain structure includes a source, a...
US-9,911,847 Non-volatile memory device and manufacturing method thereof
A non-volatile memory device includes a substrate, a gate stack structure, an erase gate structure, and a ferroelectric layer. The gate stack structure is...
US-9,911,846 Semiconductor device having a bandgap wider than that of silicon
An interlayer insulating film is formed on a gate insulating film and a gate electrode, and the interlayer insulating film is opened forming contact holes....
US-9,911,845 High voltage LDMOS transistor and methods for manufacturing the same
A semiconductor device is provided. The semiconductor device comprises a substrate, a gate, a first doped region and a second doped region. The gate is over the...
US-9,911,844 Semiconductor device
The semiconductor device includes: a semiconductor layer in which a trench is formed having a side surface and a bottom surface; a second conductivity-type...
US-9,911,843 Semiconductor device
A parasitic capacitance and a leak current in a nitride semiconductor device are reduced. For example, a 100 nm-thick buffer layer made of AlN, a 2 .mu.m-thick...
US-9,911,842 Nitride semiconductor device, production method thereof, diode, and field effect transistor
A nitride semiconductor device includes; a semiconductor stack configured with a plurality of semiconductor layers made of nitride semiconductors provided on a...
US-9,911,841 Single-electron transistor and its fabrication method
Single-electron transistor comprising at least: first semiconductor portions forming source and drain regions, a second semiconductor portion forming at least...
US-9,911,840 Self aligned trench MOSFET with integrated diode
A transistor device includes a doped semiconductor substrate having one or more electrically insulated gate electrodes formed in trenches in the substrate. One...
US-9,911,839 RB-IGBT
An RB-IGBT is provided that has a new emitter trench structure with improved breakdown voltage achieved by improving the electrical field distribution of the...
US-9,911,838 IGBT die structure with auxiliary P well terminal
An IGBT die structure includes an auxiliary P well region. A terminal, that is not connected to any other IGBT terminal, is coupled to the auxiliary P well...
US-9,911,837 Heterojunction bipolar transistor
A heterojunction bipolar transistor, comprising an elongated base mesa, an "H" shaped emitter, two base electrodes, an elongated collector, and two elongated...
US-9,911,836 Vertical ballast technology for power HBT device
Power amplification devices are disclosed having a vertical ballast configuration to prevent thermal runaway in at least one stack of bipolar transistors formed...
US-9,911,835 Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and...
Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling...
US-9,911,834 Integrated strained stacked nanosheet FET
Transistors include multiple stress liners. One or more channel structures are suspended at opposite ends from the plurality of stress liners. The stress liners...
US-9,911,833 Semiconductor structures and fabrication methods thereof
A method for fabricating a semiconductor structure includes forming a plurality of first fin structures in a peripheral region of a substrate and a plurality of...
US-9,911,832 Method to improve gate dielectric quality for FinFET
A method for manufacturing a semiconductor device includes providing a substrate structure comprising a substrate, a plurality of fins on the substrate and a...
US-9,911,831 Spacer formation on semiconductor device
A method for forming a semiconductor device comprising forming a semiconductor fin on a substrate, forming a first sacrificial gate stack over a first channel...
US-9,911,830 FinFETs with contact-all-around
An integrated circuit structure includes a semiconductor substrate, a semiconductor fin over the semiconductor substrate, a gate stack on a top surface and a...
US-9,911,829 FinFET with bottom SiGe layer in source/drain
A FinFET includes a substrate, a fin structure on the substrate, a source in the fin structure, a drain in the fin structure, a channel in the fin structure...
US-9,911,828 Methods of fabricating a semiconductor device
Provided are methods of fabricating a semiconductor device including a field effect transistor. Such methods may include sequentially forming lower and...
US-9,911,826 Devices with strained source/drain structures
A device includes a substrate, a gate structure over the substrate, and source/drain (S/D) features in the substrate and interposed by the gate structure. At...
US-9,911,825 Integrated circuits with spacer chamfering and methods of spacer chamfering
Semiconductor devices and methods for forming the devices with spacer chamfering. One method includes, for instance: obtaining a wafer with at least one source,...
US-9,911,824 Semiconductor structure with multi spacer
A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a...
US-9,911,823 POC process flow for conformal recess fill
A method of filling trenches between gates includes forming a first and a second dummy gate over a substrate, the first and second dummy gates including a...
US-9,911,822 Method for manufacturing vertically integrated semiconductor device
A vertically integrated semiconductor device in accordance with various embodiments may include: a first semiconducting layer; a second semiconducting layer...
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