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Patent # Description
US-9,911,771 Radiographic imaging array fabrication process for metal oxide thin-film transistors with reduced mask count
Embodiments of radiographic imaging systems; radiography detectors and methods for using the same; and/or fabrication methods therefore can include radiographic...
US-9,911,770 Graded-semiconductor image sensor
An image sensor includes a semiconductor material having an illuminated surface and a non-illuminated surface. A plurality of photodiodes is disposed in the...
US-9,911,769 Elevated pocket pixels, imaging devices and systems including the same and method of forming the same
An elevated photosensor for image sensors and methods of forming the photosensor. The photosensor may have light sensors having indentation features including,...
US-9,911,768 Solid state imaging device and electronic apparatus
The present disclosure relates to a solid state imaging device in which, in phase difference pixels that do not include a light blocking layer for forming a...
US-9,911,767 Manufacturing method of semiconductor device comprising oxide semiconductor
A semiconductor device using an oxide semiconductor is provided with stable electric characteristics to improve the reliability. In a manufacturing process of a...
US-9,911,766 Array substrate and manufacturing method thereof, and display apparatus
The present invention provides an array substrate and a manufacturing method thereof, and a display apparatus comprising the array substrate an array substrate,...
US-9,911,765 Thin film transistor substrate including thin film transistor formed of oxide semiconductor and method for...
A thin film transistor (TFT) located on a thin film transistor substrate includes a first insulating film formed so as to cover a gate electrode, a channel...
US-9,911,764 Display apparatus and method of manufacturing the same
A method of manufacturing a display apparatus includes separating a light-emitting diode ("LED") chip from a base substrate; disposing the separated...
US-9,911,763 Thin film transistor array substrate and display apparatus including the same
A thin film transistor array substrate comprises: a substrate; a driving thin film transistor including an active layer, a gate electrode, a source electrode,...
US-9,911,762 Display device
A display device is provided, which includes a substrate structure containing a substrate with a pixel region, and the pixel region includes an aperture region....
US-9,911,761 Thin-film transistor array substrate and organic light-emitting diode display including the same
A thin-film transistor (TFT) array substrate and organic light-emitting diode (OLED) display are disclosed. In one aspect, the TFT array substrate includes a...
US-9,911,760 Thin film transistor substrate and manufacturing method thereof
A thin film transistor substrate including a second electrode connected to a first electrode within a shared contact hole; and a fourth electrode connected to a...
US-9,911,759 Semiconductor device and display device
According to one embodiment, a semiconductor device includes first and second gate electrodes, a semiconductor layer, an output electrode, and an insulating...
US-9,911,758 Display substrate, display device and display device identification method
A display substrate, a display device and a method to identify a display device are provided. The display substrate comprises a display region and a periphery...
US-9,911,757 Semiconductor device and display device including the semiconductor device
Provided is a novel semiconductor device. The semiconductor device comprises a first transistor and a second transistor. The first transistor comprises a first...
US-9,911,756 Semiconductor device including transistor and electronic device surrounded by layer having assigned band gap to...
To provide a semiconductor device that is not easily damaged by ESD in a manufacturing process thereof. A layer whose band gap is greater than or equal to 2.5...
US-9,911,755 Semiconductor device including transistor and capacitor
A semiconductor device includes a transistor including an insulating film, an oxide semiconductor film, a gate electrode overlapping with the oxide...
US-9,911,754 3D memory structure
A process for fabricating a 3D memory is shown. Linear stacks, each of which includes alternately stacked gate lines and insulating layers, are formed. A charge...
US-9,911,753 Semiconductor device and method for manufacturing semiconductor device
According to one embodiment, an insulating layer is provided above a stairstep portion of a stacked body. A first cover film is provided between the stairstep...
US-9,911,752 Semiconductor memory device and method for manufacturing same
According to one embodiment, a semiconductor memory device includes a semiconductor substrate, a stacked body provided on the semiconductor substrate and...
US-9,911,751 Manufacturing method for semiconductor device having hole penetrating stack structure
A manufacturing method for a semiconductor device includes forming a first stacked structure, forming a first hole penetrating the first stacked structure,...
US-9,911,750 Semiconductor memory devices including asymmetric word line pads
Semiconductor memory devices may include a semiconductor substrate, a first stack disposed on the semiconductor substrate and a second stack disposed on the...
US-9,911,749 Stacked 3D semiconductor memory structure
According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate and including a plurality of electrode...
US-9,911,748 Epitaxial source region for uniform threshold voltage of vertical transistors in 3D memory devices
An alternating stack of insulating layers and sacrificial material layers are formed over a substrate. Memory stack structures are formed through the...
US-9,911,747 Integration of a memory transistor into high-k, metal gate CMOS process flow
Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors and methods of forming the same are described. Generally, the method...
US-9,911,746 Integration of a memory transistor into high-k, metal gate CMOS process flow
Memory cells including embedded SONOS based non-volatile memory (NVM) and MOS transistors are described. The memory cell includes a substrate having a...
US-9,911,745 Three-dimensionally integrated circuit devices including oxidation suppression layers
A vertically integrated circuit device can include a substrate having a first region reserved for first functional circuits of the vertically integrated circuit...
US-9,911,744 Methods and apparatus for SRAM cell structure
An SRAM cell structure. In one embodiment, a bit cell first level contacts formed at a first and a second CVdd node, a first and a second CVss node, at a bit...
US-9,911,743 Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same
Under one aspect, a method of making a nanotube switch includes: providing a substrate having a first conductive terminal; depositing a multilayer nanotube...
US-9,911,742 Semiconductor structures
A method for forming a semiconductor structure includes sequentially providing a semiconductor substrate having NFET regions and NFET regions; forming an...
US-9,911,741 Dual channel material for finFET for high performance CMOS
Silicon fins are formed in a bulk silicon substrate and thereafter trench isolation regions are formed between each silicon fin. The silicon fins in nFET and...
US-9,911,740 Method, apparatus, and system having super steep retrograde well with engineered dopant profiles
Generally, in one embodiment, the present disclosure is directed to a method for forming a transistor. The method includes: implanting a substrate to form at...
US-9,911,739 III-V FinFET CMOS with III-V and germanium-containing channel closely spaced
Closely spaced III-V compound semiconductor fins and germanium-containing semiconductor fins are provided by utilizing mandrel structures for III-V compound...
US-9,911,738 Vertical-transport field-effect transistors with a damascene gate strap
Methods for forming a structure that includes vertical-transport field-effect transistors and structures that include vertical-transport field-effect...
US-9,911,737 Integrated circuit comprising transistors with different threshold voltages
An integrated circuit includes a substrate with first and second cells having first and second FDSOI field-effect transistors. There are first and second ground...
US-9,911,736 Method of forming field effect transistors with replacement metal gates and contacts and resulting structure
In a method for forming an integrated circuit (IC) structure, which incorporates multiple field effect transistors (FETs) with discrete replacement metal gates...
US-9,911,735 Fin-like field effect transistor (FinFET) device and method of manufacturing same
A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary device includes a fin structure formed over a semiconductor substrate. The...
US-9,911,734 Semiconductor device containing HEMT and MISFET and method of forming the same
A semiconductor structure with a MISFET and a HEMT region includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V...
US-9,911,733 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device, including a semiconductor substrate, a plurality of trenches formed on a front surface of the semiconductor substrate, a plurality of...
US-9,911,732 Vertical metal insulator metal capacitor having a high-k dielectric material
A vertical metal-insulator-metal (MIM) capacitor is formed within multiple layers of a multi-level metal interconnect system of a chip. The vertical MIM...
US-9,911,731 Operational gallium nitride devices
A power circuit is described that includes a semiconductor body having a common substrate and a Gallium Nitride (GaN) based substrate. The GaN based substrate...
US-9,911,730 Transient voltage suppressor and manufacture method thereof
A transient voltage suppressor can include: a semiconductor substrate; a first buried layer of a first type formed in and on the semiconductor substrate; a...
US-9,911,728 Transient voltage suppressor (TVS) with reduced breakdown voltage
A low capacitance transient voltage suppressor with snapback control and a reduced voltage punch-through breakdown mode includes an n+ type substrate, a first...
US-9,911,727 Strapping structure of memory circuit
A memory circuit includes a first memory cell and a second memory adjacent to the first memory cell. The first memory cell includes a first word line strapping...
US-9,911,726 Method and apparatus to facilitate direct surface cooling of a chip within a 3D stack of chips using optical...
In one embodiment, the disclosure relates to a system of stacked and connected layers of circuits that includes at least one pair of adjacent layers having very...
US-9,911,725 Packaging mechanisms for dies with different sizes of connectors
Embodiments of mechanisms for forming a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical...
US-9,911,724 Multi-chip package system and methods of forming the same
In an embodiment, a semiconductor structure includes a multi-chip package system (MCPS). The MCPS includes one or more dies, a molding compound extending along...
US-9,911,723 Magnetic small footprint inductor array module for on-package voltage regulator
An apparatus comprises an inductor module including: a module substrate including a magnetic dielectric material; a plurality of inductive circuit elements...
US-9,911,722 Method and structure for receiving a micro device
A method and structure for receiving a micro device on a receiving substrate are disclosed. A micro device such as a micro LED device is punched-through a...
US-9,911,720 Power switch packaging with pre-formed electrical connections for connecting inductor to one or more transistors
In some examples, device includes an integrated circuit (IC) inside a first insulating layer, an inductor, and a second insulating layer arranged between the...
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