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Patent # Description
US-9,911,719 Semiconductor component, lighting device and method for producing a semiconductor component
The invention relates to a semiconductor component (1) comprising: a plurality of semiconductor chips (2), each having a semiconductor layer sequence (200) with...
US-9,911,718 `RDL-First` packaged microelectronic device for a package-on-package device
Methods and apparatuses relate generally to a packaged microelectronic device for a package-on-package device ("PoP") with enhanced tolerance for warping. In...
US-9,911,717 Stackable microelectronic package structures
A microelectronic assembly includes a first microelectronic package having a substrate with first and second opposed surfaces and substrate contacts thereon....
US-9,911,716 Polygon die packaging
A lidded or lidless flip-chip package includes two or more polygon shaped dies. The polygon dies may be interconnected to a substrate or to an interposer...
US-9,911,715 Three-dimensional package structure and the method to fabricate thereof
The present invention discloses a three-dimensional package structure which can achieve a relatively high utilization of an internal space thereof, so that the...
US-9,911,714 Lead frame
A lead frame includes adjacent die pads which lie adjacent to each other; grounding leads extended from the adjacent die pads; a connecting bar by which the...
US-9,911,713 Method for applying a bonding layer
A method for applying a bonding layer that is comprised of a basic layer and a protective layer on a substrate with the following method steps: application of...
US-9,911,712 Clip and related methods
A clip for a semiconductor package. Implementations may include: an electrically conductive clip having a first end and a second end and a middle section...
US-9,911,711 Structures and methods to enable a full intermetallic interconnect
A method forming an interconnect structure includes depositing a first solder bump on a chip; depositing a second solder bump on a laminate, the second solder...
US-9,911,710 Thermo-compression bonding system, subsystems, and methods of use
Co-planarity adjustment systems and methods, gantries capable of applying high force without imposing moment loads to their bearings, systems and methods for...
US-9,911,709 Semiconductor device and semiconductor manufacturing process
A semiconductor device includes a first semiconductor die, a second semiconductor die and a plurality of supporting structures. The first semiconductor die...
US-9,911,708 Conductive pillar shaped for solder confinement
A method of fabricating a pillar-type connection includes forming, on a bond pad, a first conductive layer including a hollow core. A second conductive layer is...
US-9,911,707 Structure and method of forming a pad structure having enhanced reliability
An integrated circuit structure includes a substrate, and a first metal layer over the substrate. The integrated circuit structure further includes a second...
US-9,911,706 Semiconductor device
A semiconductor device includes a main pad part and a sub pad part formed in a peripheral area of at least one side of the main pad part. The sub pad part is...
US-9,911,705 Semiconductor device and semiconductor device manufacturing method
A semiconductor device of the present invention includes a semiconductor element, a surface electrode formed on a surface of the semiconductor element, a metal...
US-9,911,703 Output impedance matching circuit for RF amplifier devices, and methods of manufacture thereof
A packaged RF amplifier device includes a transistor and an output circuit. The transistor includes a control terminal and first and second current carrying...
US-9,911,702 Semiconductor package structure and fabrication method thereof
A semiconductor package structure and a fabrication method thereof are provided. The fabrication method comprises: providing a substrate strip, the substrate...
US-9,911,701 Mark forming method and device manufacturing method
A mark forming method includes: a step of forming, on a device layer of a wafer, an intermediate layer to which a polymer layer containing a block copolymer is...
US-9,911,700 Embedded packages
A structure consisting of at least one die embedded in a polymer matrix and surrounded by the matrix, and further consisting of at least one through via through...
US-9,911,699 Semiconductor device
A graphic data of a first wiring in a first area of a semiconductor wafer may be extracted, which may correspond to a semiconductor chip forming area. The first...
US-9,911,698 Metal alloy capping layers for metallic interconnect structures
A semiconductor device is provided which comprises a metal interconnect structure having a metal alloy capping layer formed within a surface region of the metal...
US-9,911,697 Power strap structure for high performance and low current density
The present disclosure relates to an integrated chip that uses a metal strap to improve performance and reduce electromigration by coupling a ...
US-9,911,696 Packaged semiconductor assemblies and methods for manufacturing such assemblies
Packaged semiconductor assemblies including interconnect structures and methods for forming such interconnect structures are disclosed herein. One embodiment of...
US-9,911,695 Wiring board including multiple wiring layers that are different in surface roughness
A wiring board includes an insulating layer, a first wiring layer, and a second wiring layer. The first wiring layer is formed in a first surface of the...
US-9,911,694 Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed...
Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to...
US-9,911,693 Semiconductor devices including conductive lines and methods of forming the semiconductor devices
A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion,...
US-9,911,692 Conductive structures, systems and devices including conductive structures and related methods
Conductive structures include a plurality of conductive steps and a contact extending at least partially therethrough in communication with at least one of the...
US-9,911,691 Interconnection structure and manufacturing method thereof
An interconnection structure includes a first dielectric layer, at least one first conductor, and an etch stop layer. The first conductor is disposed partially...
US-9,911,690 Interconnect structures with fully aligned vias
A structure having fully aligned via connecting metal lines on different Mx levels. The structure may include a first metal line and a second metal line in a...
US-9,911,689 Through-body-via isolated coaxial capacitor and techniques for forming same
Techniques are disclosed for forming a through-body-via (TBV) isolated coaxial capacitor in a semiconductor die. In some embodiments, a cylindrical capacitor...
US-9,911,688 Semiconductor chip, semiconductor package including the same, and method of fabricating the same
A semiconductor device includes a semiconductor chip substrate with a chip region and a scribe lane region, center and boundary pads respectively provided on...
US-9,911,687 Molding compound structure
A device comprises a package component comprising a plurality of bumps formed on a first side of the package component, a semiconductor die mounted on the first...
US-9,911,686 Source down semiconductor devices and methods of formation thereof
A method for forming a semiconductor device includes forming device regions in a semiconductor substrate having a first side and a second side. The device...
US-9,911,685 Land structure for semiconductor package and method therefor
In one embodiment, a method for forming a package substrate includes selectively removing portions of a lead frame to form cavities and filling the cavities...
US-9,911,684 Holes and dimples to control solder flow
A system, in some embodiments, comprises: a first surface of a lead frame; a second surface of the lead frame, opposite the first surface, said second surface...
US-9,911,683 Film for back surface of flip-chip semiconductor
The film for back surface of flip-chip semiconductor according to the present invention is a film for back surface of flip-chip semiconductor to be formed on a...
US-9,911,682 Phase changing on-chip thermal heat sink
A method of forming an on-chip heat sink includes forming a device on a substrate. The method also includes forming a plurality of insulator layers over the...
US-9,911,681 Silicone-based thermal interface materials
In an example, a silicone-based thermal interface material includes a thermally conductive material and a silicone-based polymeric material having a solubility...
US-9,911,680 Bidirectional semiconductor package
Provided is a bidirectional semiconductor package in which the number of processes for manufacturing the bidirectional semiconductor package is reduced....
US-9,911,679 Semiconductor package with integrated output inductor on a printed circuit board
A semiconductor package includes a semiconductor die comprising a control transistor and a sync transistor, an integrated output inductor comprising a winding...
US-9,911,678 Substrate with integrated heat spreader
The present disclosure relates to a substrate with an integrated heat spreader. The disclosed substrate includes a substrate core, at least one connecting...
US-9,911,677 Element chip and method for manufacturing the same
A method for manufacturing an element chip includes a protection film etching step of removing a part of the protection film which is stacked on the dividing...
US-9,911,676 System and method for gas-phase passivation of a semiconductor surface
Improved methods and systems for passivating a surface of a high-mobility semiconductor and structures and devices formed using the methods are disclosed. The...
US-9,911,675 Packaged semiconductor devices and methods of packaging semiconductor devices
Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an...
US-9,911,674 Molding structure for wafer level package
Apparatus, and methods of manufacture thereof, in which a molding compound is formed between spaced apart microelectronic devices. The molding compound...
US-9,911,673 Semiconductor device with bond pad wiring lead-out arrangement avoiding bond pad probe mark area
Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening...
US-9,911,672 Semiconductor devices, method for fabricating integrated fan-out packages, and method for fabricating...
A semiconductor device including an integrated circuit, a plurality of conductive pillars, and a protection layer is provided. The integrated circuit includes a...
US-9,911,671 Encapsulation system and method having variable output for heating encapsulant
The present disclosure discloses an encapsulation system and an encapsulation method, the encapsulation system including a thickness detection unit, an output...
US-9,911,670 Integrated circuit including NCEM-enabled, via-open/resistance-configured fill cells, with NCEM pads formed...
An integrated circuit, in the form of a wafer, die, or chip, includes multiple standard cell-compatible fill cells, configured to enable non-contact electrical...
US-9,911,669 Integrated circuit including NCEM-enabled, diagonal gap-configured fill cells, with NCEM pads formed from at...
An integrated circuit, in the form of a wafer, die, or chip, includes multiple standard cell-compatible fill cells, configured to enable non-contact electrical...
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