Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-9,911,668 Integrated circuit including NCEM-enabled, corner gap-configured fill cells, with NCEM pads formed from at...
An integrated circuit, in the form of a wafer, die, or chip, includes multiple standard cell-compatible fill cells, configured to enable non-contact electrical...
US-9,911,667 Structure for die probing
A package includes a device die, which includes a metal pillar at a top surface of the device die, and a solder region on a sidewall of the metal pillar. A...
US-9,911,666 Apparatus and method for inspecting a semiconductor package
There is provided an apparatus and method for inspecting a semiconductor package. The apparatus includes at least one 3D camera positioned at a first angle...
US-9,911,665 Integrated circuits, methods of forming the same, and methods of determining gate dielectric layer electrical...
Integrated circuits, methods of forming integrated circuits, and methods of determining gate dielectric layer electrical thickness in integrated circuits are...
US-9,911,664 Substrate features for inductive monitoring of conductive trench depth
A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor...
US-9,911,663 Preventing buried oxide gouging during planar and FinFET processing on SOI
A method for preventing damage to the insulator layer of a semiconductor device during creation of fin field effect transistor (FinFET) includes obtaining a...
US-9,911,662 Forming a CMOS with dual strained channels
The present invention relates generally to a semiconductor device, and more particularly, to a structure and method of forming a compressive strained layer and...
US-9,911,661 Nano wire structure and method for fabricating the same
A method includes depositing a sacrificial layer on a first dielectric layer over a substrate; applying a first patterning process, a second patterning process,...
US-9,911,660 Methods for forming germanium and silicon germanium nanowire devices
A method for forming nanowire semiconductor devices includes a) providing a substrate including an oxide layer defining vias; and b) depositing nanowires in the...
US-9,911,659 Semiconductor devices and methods of fabricating the same
Semiconductor devices and methods of fabricating the same are provided. The semiconductor devices may include gate electrodes on a substrate. A longitudinal...
US-9,911,658 Methods for forming a semiconductor arrangement with multiple-height fins and substrate trenches
Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. An etch sequence is performed to...
US-9,911,657 Semiconductor device including finFET and fin varactor
A semiconductor device includes a semiconductor substrate having a fin-type field effect transistor (finFET) on a first region and a fin varactor on a second...
US-9,911,656 Wimpy device by selective laser annealing
A method for co-integrating wimpy and nominal devices includes growing source/drain regions on semiconductor material adjacent to a gate structure to form...
US-9,911,655 Method of dicing a wafer and semiconductor chip
A method of dicing a wafer may include forming a plurality of active regions in a wafer, each active region including at least one electronic component, the...
US-9,911,654 Method and apparatus for plasma dicing a semi-conductor wafer
The present invention provides a method for plasma dicing a substrate. The method comprising providing a process chamber having a wall; providing a plasma...
US-9,911,653 Low capacitance interconnect structures and associated systems and methods
Semiconductor device interconnect structures having low capacitance and associated systems and methods are disclosed herein. In one embodiment, a method of...
US-9,911,652 Forming self-aligned vias and air-gaps in semiconductor fabrication
Mandrel lines non-mandrel lines, and spacers are located in a structure having several layers. A spacer in the set of spacers comprises a structure formed above...
US-9,911,651 Skip-vias bypassing a metallization level at minimum pitch
A method of forming a skip-via, including, forming a first dielectric layer on a first metallization layer, forming a second metallization layer on the first...
US-9,911,650 Semiconductor device with an interconnect structure and method for forming the same
A method for forming a semiconductor device structure includes providing a substrate and forming a gate electrode on the substrate. A first contact structure is...
US-9,911,649 Process for making and using mesh-style NCEM pads
Wafers, chips, or dies that contain fill cells with structures configured to obtain in-line data via non-contact electrical measurements ("NCEM"). Such...
US-9,911,648 Interconnects based on subtractive etching of silver
A method for forming at least one Ag or Ag based alloy feature in an integrated circuit, including providing a blanket layer of Ag or Ag based alloy in a...
US-9,911,647 Self aligned conductive lines
A method for forming conductive lines on a wafer comprises forming a first hardmask, a planarizing layer, a second hardmask, a layer of sacrificial mandrel...
US-9,911,646 Self-aligned double spacer patterning process
Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method...
US-9,911,645 Method for forming fin field effect transistor (FinFET) device structure with interconnect structure
A method includes a first metal layer formed over a substrate and a dielectric layer formed over the first metal layer. The method includes an adhesion layer...
US-9,911,644 Semiconductor devices and methods of fabricating the same
The present disclosure describes semiconductor devices and methods of fabricating the same. The method includes forming an interlayer insulating layer on a...
US-9,911,643 Semiconductor constructions and methods of forming intersecting lines of material
Some embodiments include semiconductor constructions having first and second electrically conductive lines that intersect with one another at an intersection....
US-9,911,642 Method of manufacturing an electronic device, and electronic device manufacturing apparatus
According to this disclosure, a method of manufacturing an electronic device is provided, which includes exposing a top surface of a first electrode of a first...
US-9,911,641 Process for manufacturing a semiconductor substrate, and semiconductor substrate obtained
The invention relates to a process for manufacturing a semiconductor substrate, characterized in that it comprises providing at least one donor semiconductor...
US-9,911,640 Universal gripping and suction chuck
Proposed is a universal gripping and suction chuck for use as an interchangeable end effector of a robot arm of a robotic station capable of picking up,...
US-9,911,639 Composite substrate, elastic wave device, and method for producing elastic wave device
A composite substrate 10 is formed by bonding together a piezoelectric substrate 12 and a support substrate 14 that has a lower thermal expansion coefficient...
US-9,911,638 Plasma processing apparatus and plasma processing method
A plasma processing apparatus includes: a reaction chamber; a plasma generation unit; a stage disposed inside the reaction chamber; an electrostatic chuck...
US-9,911,637 Overlapping device, and overlapping method
An overlapping device which is configured to detect the center positions of a substrate and a support which are held in a center position detecting portion,...
US-9,911,636 Multiple diameter in-vacuum wafer handling
An electrostatic chuck and gripping system are configured for clamping and processing workpieces having differing diameters. An ion implantation apparatus...
US-9,911,635 Substrate processing apparatus, method of manufacturing semiconductor device and non-transitory...
Provided is a substrate processing apparatus including a substrate container transfer device configured to transfer a substrate container accommodating a...
US-9,911,634 Self-contained metrology wafer carrier systems
A self-contained metrology wafer carrier systems and methods of measuring one or more characteristics of semiconductor wafers are provided. A wafer carrier...
US-9,911,633 Semiconductor processing boat design with pressure sensor
Presented herein is a device processing boat comprising a base and at least one unit retainer disposed in the base. The device further comprises a cover having...
US-9,911,632 Multiple part decoration system and method
According to an aspect herein, there is provided a method of decorating multiple parts, the method includes: loading a plurality of parts onto a pallet;...
US-9,911,631 Processing system and method for providing a heated etching solution
Embodiments of the invention provide a processing system and a method for processing with a heated etching solution. In one example, tight control over...
US-9,911,630 Apparatus for treating surfaces of wafer-shaped articles
A device for processing wafer-shaped articles comprises a closed process chamber providing a gas-tight enclosure, and a rotary chuck located within the closed...
US-9,911,629 Integrated passive device package and methods of forming same
An embodiment device package includes a first die, a second die, and a molding compound extending along sidewalls of the first die and the second die. The...
US-9,911,628 Semiconductor device leadframe
For so called film assisted molding (FAM) device processing techniques there is provided lead frame for a semiconductor device, comprising a base portion and a...
US-9,911,627 Method of processing a semiconductor device
A method for processing a 3D semiconductor device, the method including: processing a first layer comprising first transistors, forming a first power...
US-9,911,625 Method for manufacturing semiconductor device
In a transistor including an oxide semiconductor layer, an oxide insulating layer is formed so as to be in contact with the oxide semiconductor layer. Then,...
US-9,911,624 Method for dissolving a silicon dioxide layer
This disclosure relates to a method for dissolving a silicon dioxide layer in a structure, including, from the back surface thereof to the front surface...
US-9,911,623 Via connection to a partially filled trench
A method includes forming a trench that is partially filled with a first metal material, the trench being formed within a first Interlayer Dielectric (ILD)...
US-9,911,622 Method of processing target object
Non-uniformity in a thickness of a silicon oxide film formed on a processing target object can be reduced even when an aspect ratio of an opening of a mask is...
US-9,911,621 Method for processing target object
This method for processing a target object includes steps ST1 to ST4. The target object has an organic polymer layer and a resist mask on a substrate. In step...
US-9,911,620 Method for achieving ultra-high selectivity while etching silicon nitride
Methods of selectively etching silicon nitride on a semiconductor substrate by providing silicon to the plasma to achieve high etch selectivity of silicon...
US-9,911,619 Fin cut with alternating two color fin hardmask
Methods for a lithographic process used to pattern fins for fin-type field-effect transistors (FinFETs). A first plurality of hardmask sections may be formed,...
US-9,911,618 Low temperature poly-silicon thin film transistor, fabricating method thereof, array substrate and display device
Embodiments of the present invention disclose a low temperature poly-silicon thin film transistor and a method of fabricating the same, an array substrate, and...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.