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Patent # Description
US-9,911,516 Cooling systems for spent nuclear fuel, casks including the cooling systems, and methods for cooling spent...
A cooling system for spent nuclear fuel may include a device configured to generate electricity using energy emitted from the spent nuclear fuel. The cooling...
US-9,911,515 Leidenpump
A non-mechanical fluid transfer device is disclosed herein. The device can include at least one tubular body configured to deliver a fluid, the tubular body...
US-9,911,514 Nuclear reactor cavity floor passive heat removal system
A nuclear reactor includes a reactor core disposed in a reactor pressure vessel. A radiological containment contains the nuclear reactor and includes a concrete...
US-9,911,513 Passive shutdown system and method of operating a liquid metal cooled reactor using the same
A passive shutdown system for a liquid metal cooled reactor may include a tube and a neutron absorber within the tube. The tube may be configured to extend...
US-9,911,512 CRDM internal electrical connector
An internal control rod drive mechanism (CRDM) including an electric motor is disposed in a nuclear reactor and further includes a support surface with sealed...
US-9,911,511 Fuel rods with wear-inhibiting coatings and methods of making the same
Nuclear reactor components are treated with thermal methods to increase wear resistance. Example treatments include thermal treatments using particulate or...
US-9,911,510 Redundancy schemes for memory cell repair
Various implementations described herein are directed to an integrated circuit having a memory cell array with multiple rows of memory cells including at least...
US-9,911,509 Counter to locate faulty die in a distributed codeword storage system
Methods and apparatus related to utilization of counter(s) for locating faulty die in a distributed codeword storage system are described. In one embodiment,...
US-9,911,508 Cache memory diagnostic writeback
A processor includes a cache memory having a plurality of entries. Each of the entries holds data of a cache line, a state of the cache line and a tag of the...
US-9,911,507 Semiconductor device, semiconductor system including the same and test method thereof
A semiconductor device includes a memory region suitable for providing a plurality of read data in parallel at every read operation cycle, an output path...
US-9,911,506 Methods for memory interface calibration
Integrated circuits with memory interface circuitry may be provided. Prior to calibration, a number of samples may be determined by computing probability...
US-9,911,505 Cost effective semiconductor devices and semiconductor systems with reduced test time
A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output a clock signal, a...
US-9,911,504 Non-volatile memory array using electromechanical switches for cell storage
A data storage cell for storing data is disclosed. In one aspect, the data storage cell comprises a first nano electromechanical switch comprising a first...
US-9,911,503 Shift register unit, gate drive circuit, and display device
The present application provides a shift register unit as well as a gate drive circuit and a display device using it. The shift register unit comprises an input...
US-9,911,502 Data storage device with nonvolatile memory
According to one embodiment, a data storage device includes a controller driven by a first power supply voltage, a nonvolatile memory controlled by the...
US-9,911,501 Sensing amplifier comprising a built-in sensing offset for flash memory devices
The present invention relates to an improved sensing amplifier and related method for use in read operations in flash memory devices. In one embodiment, the...
US-9,911,500 Dummy voltage to reduce first read effect in memory
Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage (Vth) of a memory cell can shift depending on...
US-9,911,499 Semiconductor memory device and memory system
According to one embodiment, a semiconductor memory device includes first and second memory cells, a word line, and first and second bit lines. The first and...
US-9,911,498 Semiconductor memory device and writing operation method thereof
A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command...
US-9,911,497 Three-dimensional vertical NOR flash thin-film transistor strings
A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the...
US-9,911,496 Associative memory for realizing a k-nearest neighbors algorithm
A k-nearest neighbors associative memory includes: a clock counting type associative memory that holds R pieces of reference data and outputs, for each of the R...
US-9,911,495 Memory cell having resistive and capacitive storage elements
A technique including using an array of memory cells for data storage. A given cell of the memory cells includes a capacitive storage element and a resistive...
US-9,911,494 Overlapping write schemes for cross-point non-volatile memory devices
A storage device includes an interface, NVM device, and control module. The control module may be configured to receive a first write operation and a second...
US-9,911,493 Semiconductor memory device including semi-selectable memory cells
A semiconductor memory device includes a memory cell array having first wires, a second wire, and memory cells connected to the first and second wires, and a...
US-9,911,492 Writing multiple levels in a phase change memory using a write reference voltage that incrementally ramps over...
Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally...
US-9,911,491 Determining a resistance state of a cell in a crossbar memory array
According to an example, in a method for determining a resistance state of a cell in a crossbar memory array, a first read voltage may be applied across a cell...
US-9,911,490 Memory controllers
A memory controller includes a voltage control module that operates to isolate a target memristor of a memory crossbar array. The voltage control module applies...
US-9,911,489 Memory cells, memory systems, and memory programming methods
Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically...
US-9,911,488 Three dimensional non-volatile memory with shorting source line/bit line pairs
A non-volatile storage system dedicates a subset of blocks to be used for shorting source lines to bit lines at periodic positions along the bit lines during...
US-9,911,487 Method and system for storing and recovering data from flash memory
Embodiments of the technology relate to storing user data and metadata in persistent storage in the event of a power failure and then recovering such stored...
US-9,911,486 Synchronous random access memory (SRAM) chip and two port SRAM array
A static random access memory (SRAM) chip includes a first and second conductor, a set of SRAM cells and a set of first and second tracking cells. The first...
US-9,911,485 Method and apparatus for refreshing a memory cell
A method includes sending a first signal from a memory device to a memory controller. The first signal indicates to the memory controller that particular memory...
US-9,911,484 Oscillator controlled random sampling method and circuit
Various embodiments comprise methods and apparatuses for selecting a randomly-chosen seed row from among a stream of available data in a memory system. A...
US-9,911,483 Thermally-assisted spin transfer torque memory with improved bit error rate performance
Embodiments of the invention are directed to a magnetic tunnel junction (MTJ) storage element having a reference layer formed from a reference layer material...
US-9,911,482 Method and apparatus for adjustment of current through a magnetoresistive tunnel junction (MTJ) based on...
A non-volatile memory system includes a first circuit and a second circuit both coupled to a magnetoresistance tunnel junction (MTJ) cell to substantially...
US-9,911,481 Selection circuit with autobooting for magnetic memory and methods therefor
A selection circuit and related access circuitry that can be used for column selection in spin-torque magnetic memory is disclosed. The selection circuit can be...
US-9,911,480 Semiconductor device chip selection
A method for accessing a plurality of DRAM devices each having a plurality of banks, the plurality of DRAM devices being interconnected to receive common...
US-9,911,479 Semiconductor memory device outputting read-busy signal and memory system including the same
A semiconductor memory device includes a plurality of memory cells; a peripheral circuit suitable for controlling the memory cells, and operating in first and...
US-9,911,478 Method and apparatus for auto-calibration of delay settings of memory interfaces
In some aspects, a calibration method includes performing a write/read test for each one of multiple combinations of write/read delay settings, wherein each one...
US-9,911,477 Memory controller architecture with improved memory scheduling efficiency
Integrated circuits that include memory interface and controller circuitry for communicating with external memory are provided. The memory interface and...
US-9,911,476 Systems and methods for voice data processing
Systems and methods are provided for voice data processing. For example, a first data packet included in voice data transmitted by a client is received; the...
US-9,911,475 Semiconductor device which performs an active operation
A semiconductor device includes an information signal conversion circuit suitable for generating a flag signal from an external control signal in response to an...
US-9,911,474 Feedback circuit at word line ends
Devices include an array of memory cells arranged in rows and columns. Wordlines are connected to the memory cells, and each of the wordlines is connected to a...
US-9,911,473 Circuit with self-adjust pre-charged global data line
In some embodiments, a memory device includes a memory bank, a global data line, a first tri-state unit, a latch, a second tri-state unit and a pre-charge unit....
US-9,911,472 Write bitline driver for a dual voltage domain
Systems and methods are directed to managing signals in a dual voltage domain comprising a high voltage domain and a low voltage domain. A write bitline driver...
US-9,911,471 Input buffer circuit
Apparatuses for receiving an input signal in a semiconductor device are described. An example apparatus includes: a first amplifier that provides first and...
US-9,911,470 Fast-bypass memory circuit
A memory circuit that presents input data at a data output promptly on receiving a clock pulse includes upstream and downstream memory logic and selection...
US-9,911,469 Apparatuses and methods for power efficient driver circuits
An apparatus comprising is disclosed. The apparatus a driver circuit configured to selectively provide a first supply voltage to an output node in a first...
US-9,911,468 Memory with deferred fractional row activation
Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption....
US-9,911,467 Resistance variable memory apparatus and operating method thereof
A resistance variable memory apparatus may include a memory cell array and a controller. The memory cell array may include a plurality of resistance variable...
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