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Patent # Description
US-9,910,802 High bandwidth low latency data exchange between processing elements
Direct communication of data between processing elements is provided. An aspect includes sending, by a first processing element, data over an inter-processing...
US-9,910,801 Processor model using a single large linear registers, with new interfacing signals supporting FIFO-base I/O...
A processor or CPU architecture that implements many enabling technologies proven to enhance data through put supporting the synchronous burst data transfer....
US-9,910,800 Utilizing remote direct memory access (`RDMA`) for communication between controllers in a storage array
Emulating a remote direct memory access (`RDMA`) link between controllers in a storage array, including: inserting, into a buffer utilized by a direct memory...
US-9,910,799 Interconnect distributed virtual memory (DVM) message preemptive responding
Aspects include computing devices, apparatus, and methods for accelerating distributive virtual memory (DVM) message processing in a computing device. DVM...
US-9,910,798 Storage controller cache memory operations that forego region locking
Methods and structure for managing cache memory for a storage controller. One exemplary embodiment a Redundant Array of Independent Disks (RAID) storage...
US-9,910,797 Space efficient formats for scatter gather lists
Methods and structure for formatting and processing Scatter Gather Lists (SGLs). One exemplary embodiment is a storage controller that includes a cache memory...
US-9,910,796 Programmable event driven yield mechanism which may activate other threads
Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes...
US-9,910,795 Access of virtual machines to storage area networks
A method for managing access of virtual machines executed by a host computer system to storage area networks, the storage area networks connecting the host...
US-9,910,794 Processing data
A method for executing a program code is suggested, the method comprising: checking a memory access policy resource based on a trigger; and comparing a current...
US-9,910,793 Memory encryption engine integration
Memory encryption engine (MEE) integration technologies are described. A MEE system may include a MEE interface and a MEE core. The MEE interface may receive a...
US-9,910,792 Composite field scaled affine transforms-based hardware accelerator
A processing system includes a memory and a cryptographic accelerator operatively coupled to the memory. The cryptographic accelerator performs a split...
US-9,910,791 Managing system-wide encryption keys for data storage systems
The techniques presented herein provide for initializing and upgrading data encryption capability in a data storage system. The data storage system in...
US-9,910,790 Using a memory address to form a tweak key to use to encrypt and decrypt data
Provided are a memory system, memory controller, and method for using a memory address to form a tweak key to use to encrypt and decrypt data. A base tweak co...
US-9,910,789 Electrical and optical memory access
A processor issues a command to a memory through an electrical memory link and performs a process according to the command through the electrical memory link....
US-9,910,788 Cache access statistics accumulation for cache line replacement selection
A processor device includes a cache and a memory storing a set of counters. Each counter of the set is associated with a corresponding block of a plurality of...
US-9,910,787 Virtual address table
The present disclosure includes apparatuses and methods related to virtual address tables. An example method comprises generating an object file that comprises:...
US-9,910,786 Efficient redundant array of independent disks (RAID) write hole solutions
Disclosed are solutions for resolving a redundant array of independent disks (RAID) write hole, or a parity-based fault scenario that occurs when a power...
US-9,910,785 Cache memory budgeted by ways based on memory access type
A set associative cache memory, comprising: an array of storage elements arranged as N ways; an allocation unit that allocates the storage elements of the array...
US-9,910,784 Methods and systems for directly mapping a backend block address into a physical address of a caching device
A storage device made up of multiple storage media is configured such that one such media serves as a cache for data stored on another of such media. The device...
US-9,910,782 Expedited servicing of store operations in a data processing system
In at least some embodiments, a processor core generates a store operation by executing a store instruction in an instruction sequence. The store operation is...
US-9,910,781 Page table including data fetch width indicator
Embodiments relate to a page table including a data fetch width indicator. An aspect includes allocating a memory page in a main memory to an application....
US-9,910,780 Pre-loading page table cache lines of a virtual machine
Embodiments herein pre-load memory translations used to perform virtual to physical memory translations in a computing system that switches between virtual...
US-9,910,779 Arithmetic processing apparatus and control method therefor
An arithmetic processing apparatus has OS arithmetic processing unit executing instruction of OS, general-purpose arithmetic processing units each executing an...
US-9,910,778 Operation processing apparatus and control method of operation processing apparatus
An operation processing apparatus includes: processor cores configured to perform an operation processing; cache memories each provided for the respective...
US-9,910,777 Enhanced integrity through atomic writes in cache
A system and method facilitate processing atomic storage requests. The method includes receiving, from a storage client, an atomic storage request for a first...
US-9,910,776 Instruction ordering for in-progress operations
Execution of the memory instructions is managed using memory management circuitry including a first cache that stores a plurality of the mappings in the page...
US-9,910,775 Computing system with adaptive back-up mechanism and method of operation thereof
A computing system includes: an adaptive back-up controller configured to calculate an adaptive back-up time based on a reserve power source for backing up a...
US-9,910,774 Spontaneous reconfiguration of data structures using balloon memory allocation
Systems for memory management in virtual machines. A method embodiment forms a reconfigurable multi-level data structure by requesting reserved memory as well...
US-9,910,773 Method and system for compacting data in non-volatile memory
A system and method for compacting data in a non-volatile memory system that may reduce the need for control data updates is described. The method may include...
US-9,910,772 Flash memory apparatus and storage management method for flash memory
A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell...
US-9,910,771 Non-volatile memory interface
In an embodiment, a memory interface may send an indication that a request is being sent. The indication may be sent to a non-volatile memory via a...
US-9,910,770 Microcomputer having processor capable of changing endian based on endian information in memory
There is a need to provide a microcomputer capable of eliminating an external terminal for endian selection. Flash memory includes a user boot area for storing...
US-9,910,769 Alignment based block concurrency for accessing memory
Embodiments relate to accessing data in a memory. A method for accessing data in a memory coupled to a processor is provided. The method receives a memory...
US-9,910,768 Method for memory management for virtual machines
A method and system for management of physical memory of Virtual Machines (VMs) using dynamic memory reallocation based on estimated usages by each of the VMs...
US-9,910,767 Leveraging instruction RAM as a data RAM extension during use of a modified Harvard architecture processor
On-chip instruction RAM is leveraged as an extension of on-chip data RAM during normal use of a modified Harvard Architecture processor. Unused space in an...
US-9,910,766 Whitebox network fuzzing
Software testing of networked devices using whitebox fuzzing is provided. Target network device (TC) can execute a software target that can selectively receive...
US-9,910,765 Providing testing environments for software applications using virtualization and a native hardware layer
Methods, systems, computer-readable media, and apparatuses for providing testing environments using virtualization are presented. In one or more embodiments, a...
US-9,910,764 Automated software testing
Disclosed in some examples are systems, machine readable mediums and methods which automate testing of web-based application code by automatically generating...
US-9,910,763 Test case reduction in application binary interface (ABI) compatibility testing
A method and a system of test case reduction in application binary interface (ABI) compatibility testing are provided. The computer-implemented method includes...
US-9,910,762 Unified sandbox
A system that manages a unified sandbox environment activates a plurality of components in the unified sandbox environment, each component being configured to...
US-9,910,761 Visually debugging robotic processes
Methods, apparatus, systems, and computer-readable media are provided for visually debugging robotic processes. In various implementations, a graphical user...
US-9,910,760 Method and apparatus for interception of synchronization objects in graphics application programming interfaces...
An aspect of the present invention proposes a solution for correctly intercepting, capturing, and replaying tasks (such as functions and methods) in an...
US-9,910,759 Logging framework and methods
A system comprising one or more processors executing a first process and a second process, a memory storing log information for the first process and the second...
US-9,910,758 Computer flight recorder with active error detection
A method, apparatus and program product utilize a flight recorder having active error detection functionality to proactively detect errors in a computer or a...
US-9,910,757 Semiconductor device, log acquisition method and electronic apparatus
A semiconductor device includes a CPU access detection unit configured to detect a predetermined access among accesses from a CPU to the semiconductor device,...
US-9,910,756 Response-time baselining and performance testing capability within a software product
A method of measuring performance of a computerized system is provided. A test component integrated in a client application module is configured to generate an...
US-9,910,755 Retrieval of authoritative measurement data from in-memory datastores
A computing resource monitoring service receives a request to retrieve measurement data for a metric. The computing resource monitoring service determines,...
US-9,910,754 Duplexed control system and control method thereof
A duplexed control system comprises: two control devices, whereof one is set to operate as a reserve system and the other is set to operate as a regular system;...
US-9,910,753 Switchless fabric based atomics via partial-proxy
A data storage system has first and second computing nodes that are interconnected by a switchless fabric. Each storage node includes first and second paired...
US-9,910,752 Reliable map-reduce communications in a decentralized, self-organizing communication orbit of a distributed network
Method and system for providing message communications with failure detection and recovery are disclosed. At a respective node of a non-static collection of...
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