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Patent # Description
US-9,922,876 Interconnect structure and fabricating method thereof
An interconnect structure including a substrate, a dielectric layer, a first conductive pattern, and a second conductive pattern is provided. The dielectric...
US-9,922,875 Conductive interconnect structures incorporating negative thermal expansion materials and associated systems,...
Semiconductor devices having interconnects incorporating negative expansion (NTE) materials are disclosed herein. In one embodiment a semiconductor device...
US-9,922,874 Methods of enhancing polymer adhesion to copper
A method of processing a semiconductor substrate includes: immersing a substrate in a first bath, wherein the substrate comprises a barrier layer, a conductive...
US-9,922,873 High speed, high density, low power die interconnect system
A system for interconnecting at least two die each die having a plurality of conducting layers and dielectric layers disposed upon a substrate which may include...
US-9,922,872 Tungsten films by organometallic or silane pre-treatment of substrate
Processing methods comprising exposing a substrate to a nucleation promoter followed by sequential exposure of a first reactive gas comprising a...
US-9,922,871 Process for producing a contact on an active zone of an integrated circuit, for example produced on an SOI...
An integrated circuit includes an active zone lying above a semiconductor substrate. A cavity borders the active zone and extends, in an insulating zone, as far...
US-9,922,870 Method for applying an image of an electrically conductive material onto a recording medium and device for...
The invention relates to a method for applying an image of an electrically conductive material onto a recording medium. In the method, the recording medium is...
US-9,922,869 Electromagnetic radiation emitters and conduit structures
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
US-9,922,868 Integrated circuits using silicon on insulator substrates and methods of manufacturing the same
Integrated circuits and methods for manufacturing the same are provided. A method for producing an integrated circuit includes forming a deep isolation block in...
US-9,922,867 Method for transferring a useful layer
A method for transferring a useful layer onto a carrier substrate comprises formation of an embrittlement plane by implantation of light species into a first...
US-9,922,866 Enhancing robustness of SOI substrate containing a buried N.sup.+ silicon layer for CMOS processing
A silicon buffer layer selected from undoped silicon, p-doped silicon or a multilayered stack of, in any order, undoped silicon and p-doped silicon is provided...
US-9,922,865 Semiconductor device and manufacturing method thereof
A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes: a deep trench in a substrate; a sidewall insulating...
US-9,922,864 Trench separation diffusion for high voltage device
A manufacturable and economically viable edge termination structure allows a semiconductor device to withstand a very high reverse blocking voltage (for...
US-9,922,863 Susceptor having a hollow in its wall facing the orientation flat of a semiconductor wafer
A susceptor for securing a semiconductor wafer with an orientation flat within a pocket of the susceptor is disclosed. The pocket provides a first inner wall...
US-9,922,862 Device and method for loosening a first substrate
A device for detaching a first substrate from a second substrate in a detaching direction (L) with: at least two elements guided crosswise to the detaching...
US-9,922,861 Substrate gripping device and substrate processing apparatus
A rotary table; a drive motor M configured to rotate the rotary table; a pin base supported by the rotary table; a pin fixing member configured to move closer...
US-9,922,860 Apparatus and methods for wafer chucking on a susceptor for ALD
Described are apparatus and methods for processing a semiconductor wafer so that the wafer remains in place during processing. The wafer is subjected to a...
US-9,922,859 Joining device and joining system
A joining device for joining substrates together includes a first holding member configured to vacuum-suck a first substrate to draw and hold the first...
US-9,922,858 Semiconductor device manufacturing method
Provided is a semiconductor device manufacturing method that includes joining a support substrate to a back side of a semiconductor wafer across a ceramic...
US-9,922,857 Electrostatically clamped edge ring
An edge ring is provided for use with an electrostatic wafer chuck and an electrostatic ring chuck with a central aperture with a cooling groove and with ring...
US-9,922,856 Electrostatic heating substrate holder which is polarised at high voltage
The present invention relates to a support comprising: an electrically conductive biased table (10) connected to a high voltage power supply (12) and...
US-9,922,855 Method for reducing temperature transition in an electrostatic chuck
A method for controlling a substrate temperature in a substrate processing system includes determining a temperature difference between the substrate...
US-9,922,854 Vertical inline CVD system
The present invention generally relates to a vertical CVD system having a processing chamber that is capable of processing multiple substrates. The multiple...
US-9,922,853 Die supply apparatus
A magazine lifting and lowering section of a die supply apparatus houses a replaced magazine rack having different specifications. A code display portion marked...
US-9,922,852 Pressure calibration jig and substrate processing apparatus
The invention simplifies airbag calibration. A pressure calibration jig calibrates pressure to be applied to a plurality of airbags disposed inside a top ring...
US-9,922,851 Gas-controlled bonding platform for edge defect reduction during wafer bonding
A wafer bonding method includes placing a top wafer on a top bonding framework including a plurality of outlet holes around a periphery of the top bonding...
US-9,922,850 Apparatus for treating substrate
Disclosed is a substrate treating apparatus which includes a treating container having a treating space therein and including a plurality of collecting vessels...
US-9,922,849 Substrate liquid processing apparatus having nozzle with multiple flow paths and substrate liquid processing...
Disclosed is a substrate liquid processing apparatus. The substrate liquid processing apparatus includes a processing unit, a nozzle, a silylation liquid supply...
US-9,922,848 Apparatus for and method of processing substrate
A rinsing liquid adheres to a substrate subjected to a cleaning process. The rinsing liquid on the substrate is first replaced with IPA liquid. While the...
US-9,922,847 Microelectronics package with inductive element and magnetically enhanced mold compound component
The present disclosure relates to a microelectronics package with an inductive element and a magnetically enhanced mold compound component, and a process for...
US-9,922,846 Method of manufacturing semiconductor package
A method of manufacturing a semiconductor package includes preparing a package substrate including a semiconductor chip mounting region. A semiconductor chip is...
US-9,922,845 Semiconductor package and fabrication method thereof
A method for fabricating a semiconductor package is disclosed. A substrate is provided and a first passivation layer is formed on the substrate. Trenches are...
US-9,922,844 Semiconductor package and method for fabricating base for semiconductor package
The invention provides a semiconductor package and a method for fabricating a base for a semiconductor package. The semiconductor package includes a base. The...
US-9,922,843 Semiconductor package with multiple molding routing layers and a method of manufacturing the same
Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing...
US-9,922,842 Heat treatment method
A method for heat treatment of a plurality of semiconductor wafers horizontally placed on a supporting member coated with SiC in a vertical heat treatment...
US-9,922,841 Plasma processing method
A plasma processing method uses a plasma processing apparatus including a processing chamber, a mounting table provided in the processing chamber and configured...
US-9,922,840 Adjustable remote dissociation
Methods of selectively etching an exposed portion of a patterned substrate relative to a second exposed portion are described. The etching process is a gas...
US-9,922,839 Low roughness EUV lithography
Provided herein are methods and related apparatus to smooth the edges of features patterned using extreme ultraviolet (EUV) lithography. In some embodiments, at...
US-9,922,838 Selective, electrochemical etching of a semiconductor
Methods for facilitating fabricating semiconductor structures are provided which include: providing a multilayer structure including a semiconductor layer, the...
US-9,922,837 Asymmetric application of pressure to a wafer during a CMP process
A method includes measuring a topography of a wafer, determining that a first portion of the wafer has a greater thickness than a specified thickness. The...
US-9,922,836 Semiconductor device manufacturing method and semiconductor device
A semiconductor device manufacturing method of present application includes a catalytic step of depositing catalytic metal on a surface of a semiconductor...
US-9,922,835 Plating method, plating apparatus, and storage medium
A Plating method includes a first plating process S21 of supplying a first plating liquid to a substrate 2 having a recess 12 and forming a first plating layer...
US-9,922,834 Semiconductor device and fabrication method thereof
A semiconductor device includes first fin-shaped structures and second fin-shaped structures, which are separately disposed on a semiconductor substrate. Each...
US-9,922,833 Charge trapping split gate embedded flash memory and associated methods
Semiconductor devices and methods of manufacturing such devices are described herein. According to embodiments, the semiconductor device can be made by forming...
US-9,922,832 Manufacturing method of semiconductor structure
A manufacturing method of a semiconductor structure is provided. The manufacturing method of the semiconductor structure includes the following steps: providing...
US-9,922,831 Asymmetric high-k dielectric for reducing gate induced drain leakage
An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes...
US-9,922,830 Hybrid III-V technology to support multiple supply voltages and off state currents on same chip
Techniques for forming dual III-V semiconductor channel materials to enable fabrication of different device types on the same chip/wafer are provided. In one...
US-9,922,829 Semiconductor device and manufacturing method thereof
In a silicon carbide semiconductor device having a trench type MOS gate structure, the present invention makes it possible to inhibit the operating...
US-9,922,828 Apparatus and method for FinFETs
A method comprises performing a surface treatment on a plurality of recesses in a substrate to form a first cloak-shaped recess, a second cloak-shaped recess...
US-9,922,827 Method of forming a semiconductor structure
A method of cleaning a semiconductor structure includes rotating a semiconductor structure. The method of cleaning further includes cleaning the semiconductor...
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