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Patent # Description
US-9,929,182 Semiconductor structure and fabrication method thereof
A method is provided for fabricating a semiconductor structure. The method includes providing a bottom substrate having a first region and a second region, and...
US-9,929,181 Method for manufacturing an electronic device and method for operating an electronic device
According to various embodiments, an electronic device may include a carrier including at least a first region and a second region being laterally adjacent to...
US-9,929,180 Semiconductor device
Provided is a semiconductor device including a substrate with a plurality of logic cells, transistors provided in the plurality of logic cells, contact plugs...
US-9,929,179 Nonvolatile semiconductor devices including non-circular shaped channel patterns and methods of manufacturing...
A non-volatile memory structure can include a substrate extending horizontally and a filling insulating pattern extending vertically from the substrate. A...
US-9,929,178 Semiconductor device and method for manufacturing the same
A method for manufacturing a semiconductor device includes forming a first semiconductor layer, forming a stacked body including alternately formed first and...
US-9,929,177 Semiconductor memory device and method for manufacturing same
A semiconductor memory device includes a first semiconductor layer; a stacked body including a plurality of electrode layers stacked in a first direction; a...
US-9,929,176 Non-volatile storage device and method of manufacturing the same
According to an embodiment, a non-volatile storage device includes a first layer, a second layer formed on the first layer, a stacked body including a plurality...
US-9,929,175 Stack of horizontally extending and vertically overlapping features, methods of forming circuitry components,...
A method of forming circuitry components includes forming a stack of horizontally extending and vertically overlapping features. The stack has a primary portion...
US-9,929,174 Three-dimensional memory device having non-uniform spacing among memory stack structures and method of making...
An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures including a memory film and a...
US-9,929,173 Method of controlling a semiconductor memory device
According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory...
US-9,929,172 Method of verifying layout of vertical memory device
A method of verifying a layout of a vertical memory device includes classifying a plurality of channel holes included in the layout of the vertical memory...
US-9,929,171 Semiconductor memory device and method of manufacturing the same
A semiconductor memory device according to an embodiment comprises: a semiconductor substrate; a semiconductor layer provided extending in a first direction...
US-9,929,170 Semiconductor device
Provided herein is a semiconductor device. The semiconductor device may include a substrate, conductive patterns, and a pipe gate. The substrate may have first...
US-9,929,169 Semiconductor device and method for manufacturing the same
According to one embodiment, the stacked body includes a plurality of electrode films stacked with an insulating body. The insulating body includes a first...
US-9,929,168 Embedded memory and methods of forming the same
A method for forming an embedded flash memory device includes a gate stack, and source and drain regions in the semiconductor substrate is disclosed. The first...
US-9,929,167 Semiconductor device and manufacturing method thereof
A semiconductor device includes a non-volatile memory and a logic circuit. The non-volatile memory includes a stacked structure comprising a first insulating...
US-9,929,166 Semiconductor device
The semiconductor device according to the embodiments comprises: a plurality of first conductive layers arranged in a first direction above a substrate, the...
US-9,929,165 Method for producing integrated circuit memory cells with less dedicated lithographic steps
Methods of producing integrated circuits are provided. An exemplary method includes patterning a source line photoresist mask to overlie a source line area of a...
US-9,929,164 Integrated circuit and method for manufacturing thereof
A method for manufacturing an integrated circuit includes following steps. A substrate including a memory region and a core region is provided. At least two...
US-9,929,163 Selective epitaxy growth for semiconductor devices with fin field-effect transistors (FinFET)
A method for forming a semiconductor device includes depositing spacer material on a first sidewall and a second sidewall of a fin formed on a substrate. An...
US-9,929,162 Semiconductor device and method for forming the same
A semiconductor device include a substrate including at least a memory cell region formed thereon, an isolation mesh formed on the substrate; and a plurality of...
US-9,929,161 Complementary bipolar SRAM
A method of forming a complementary lateral bipolar SRAM device. The device includes: a first set and second set of lateral bipolar transistors forming a...
US-9,929,160 Semiconductor devices and methods of manufacturing the same
Disclosed are semiconductor devices including a field effect transistor and methods of manufacturing the same. The semiconductor device comprises a device...
US-9,929,159 Method, apparatus, and system having super steep retrograde well with silicon and silicon germanium fins
At least one method, apparatus and system disclosed involves forming a finFET device having silicon and silicon germanium fins. The method includes: forming an...
US-9,929,158 Systems and methods for integrating different channel materials into a CMOS circuit by using a semiconductor...
A method includes providing a first substrate having first and second regions, fabricating over the first region of the first substrate a channel of a first...
US-9,929,157 Tall single-fin fin-type field effect transistor structures and methods
Disclosed are methods of forming improved fin-type field effect transistor (FINFET) structures and, particularly, relatively tall single-fin FINFET structures...
US-9,929,156 Semiconductor device having dummy active fin patterns
A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and...
US-9,929,155 Semiconductor device having symmetric and asymmetric active fins
A semiconductor device and a method of manufacturing the same are disclosed, which may improve the operating performance of a multi-gate transistor in a highly...
US-9,929,154 Fin shape structure
A fin shaped structure and a method of forming the same. The method includes providing a substrate having a first fin structure and a second fin structure....
US-9,929,153 Method of making a FinFET device
A method of fabricating a fin-like field-effect transistor (FinFET) device is disclosed. The method includes forming a mandrel features over a substrate, the...
US-9,929,152 Vertical transistors and methods of forming same
One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include a fin having a first source/drain region...
US-9,929,151 Self-balanced diode device
A self-balanced diode device includes a substrate, a doped well, at least one first conductivity type heavily doped fin and at least two second conductivity...
US-9,929,150 Polysilicon diode bandgap reference
Representative implementations of devices and techniques provide a bandgap reference voltage using at least one polysilicon diode and no silicon diodes. The...
US-9,929,149 Using inter-tier vias in integrated circuits
Various implementations described herein may be directed to using inter-tier vias (IVs) in integrated circuits (ICs). In one implementation, a three-dimensional...
US-9,929,148 Semiconductor device including buried capacitive structures and a method of forming the same
The present disclosure provides semiconductor devices and manufacturing techniques in which a buried capacitive structure may be provided at the level of the...
US-9,929,147 High density capacitors formed from thin vertical semiconductor structures such as FinFETs
A vertical structure may be manufactured in a substrate of an integrated circuit, and that vertical structure used to form a high density capacitance for the...
US-9,929,146 Method of forming MOS and bipolar transistors
Bipolar transistors and MOS transistors are formed in a common process. A semiconductor layer is arranged on an insulating layer. On a side of the bipolar...
US-9,929,145 Bipolar transistor compatible with vertical FET fabrication
Integrated chips includes a first transistor and a second transistor. The first transistor includes a first semiconductor fin having a channel region and a gate...
US-9,929,144 Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor
An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal...
US-9,929,143 N-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD)
One or more techniques or systems for forming an n-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD) are provided herein. In...
US-9,929,142 Apparatus and methods for overvoltage switches with active leakage current compensation
Apparatus and methods for overvoltage switches with active leakage current compensation are provided. In certain configurations, an IC includes an input node...
US-9,929,141 Devices with an embedded zener diode
In one aspect, a silicon-controlled rectifier (SCR) includes a Zener diode embedded in the SCR. In another aspect, a laterally diffused metal oxide...
US-9,929,140 Isolation structure for IC with EPI regions sharing the same tank
An ESD cell includes an n+ buried layer (NBL) within a p-epi layer on a substrate. An outer deep trench isolation ring (outer DT ring) includes dielectric...
US-9,929,139 Modular electrostatic discharge (ESD) protection
In an embodiment, an integrated circuit (IC) may include a circuit block that couples to one or more pins of the IC to communicate and/or receive power on the...
US-9,929,136 Process for making and using a semiconductor wafer containing first and second DOEs of standard cell...
A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOES), each comprised of at least two fill...
US-9,929,135 Apparatuses and methods for semiconductor circuit layout
Apparatuses including circuit layout regions of a semiconductor device and methods of designing the circuit layout regions of a semiconductor device are...
US-9,929,134 Semiconductor device and method for filling patterns
A semiconductor device is disclosed. The semiconductor device includes: a substrate having a cell region defined thereon, in which the cell region includes a...
US-9,929,133 Semiconductor logic circuits fabricated using multi-layer structures
Systems and methods are provided for fabricating a semiconductor device structure. An example semiconductor device structure includes a first device layer, a...
US-9,929,132 Semiconductor device and process of making the same
A semiconductor device includes a substrate, a seed layer, a first patterned metal layer, a dielectric layer and a second metal layer. The seed layer is...
US-9,929,131 Method of fabricating a semiconductor package having mold layer with curved corner
A method of fabricating a semiconductor package includes mounting a plurality of semiconductor chips on a substrate in a stripped state, forming a mold layer to...
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