Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-9,929,130 Chip on chip attach (passive IPD and PMIC) flip chip BGA using new cavity BGA substrate
An integrated passive device and power management integrated circuit are directly connected, active surface to active surface, resulting in a pyramid die stack....
US-9,929,129 Array substrate of organic light-emitting diodes and method for packaging the same
An array substrate of organic light-emitting diodes and a method for fabricating the same are provided to narrow an edge frame of product device of organic...
US-9,929,128 Chip package structure with adhesive layer
A chip package structure is provided. The chip package structure includes a redistribution structure. The chip package structure includes a first chip over the...
US-9,929,127 Package including a plurality of stacked semiconductor devices an interposer and interface connections
A package can include first, second, and third dynamic random access memory (DRAM) semiconductor devices having first, second and third through vias,...
US-9,929,126 Packages with metal line crack prevention design
A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of metal pads electrically coupled to...
US-9,929,125 Flip chip module with enhanced properties
A flip chip module having at least one flip chip die is disclosed. The flip chip module includes a carrier having a top surface with a first mold compound...
US-9,929,124 Method for bonding substrates
A method for bonding a first substrate with a second substrate by means of a connecting layer that is arranged between the substrates and that is comprised of a...
US-9,929,123 Resonant circuit including bump pads
Aspects of this disclosure relate to a first die includes an LC resonant circuit including a first capacitive element, such as a capacitor or a varactor, and an...
US-9,929,122 Ribbon bonding tools and methods of using the same
A ribbon bonding tool including a body portion is provided. The body portion includes a tip portion. The tip portion includes a working surface between a front...
US-9,929,121 Bonding machines for bonding semiconductor elements, methods of operating bonding machines, and techniques for...
A method of operating a bonding machine is provided. The method includes the steps of: (a) carrying a semiconductor element with a transfer tool; and (b)...
US-9,929,120 Semiconductor device and its manufacturing method
A semiconductor device includes an opening and a redistribution layer gutter which are formed integrally in a polyimide resin film of a single layer. A...
US-9,929,119 High density substrate routing in BBUL package
Discussed generally herein are devices that include high density interconnects between dice and techniques for making and using those devices. In one or more...
US-9,929,118 Packaging through pre-formed metal pins
A package includes first package component and a second package component. The first package component includes a first electrical connector at a surface of the...
US-9,929,117 Electronic component package and electronic device including the same
An electronic component package includes an electronic component, a redistribution layer electrically connected to the electronic component and having terminal...
US-9,929,116 Electronic device module and method of manufacturing the same
The electronic device module includes a sealing part sealing an electronic component therein, and an external connection terminal disposed on one surface of the...
US-9,929,115 Device with optimized thermal characteristics
A semiconductor device includes a semiconductor substrate, a conductive pad on the semiconductor substrate, and a conductor over the conductive pad. The...
US-9,929,114 Bonding pad structure having island portions and method for manufacturing the same
A bonding pad structure is provided. The structure includes a dielectric layer on a substrate. A bonding pad is disposed on the dielectric layer and a first...
US-9,929,113 Semiconductor package and manufacturing method thereof
A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a...
US-9,929,112 Semiconductor device and method of manufacture
A redistribution layer with a landing pad is formed over a substrate with one or more mesh holes extending through the landing pad. The mesh holes may be...
US-9,929,111 Method of manufacturing a layer structure having partially sealed pores
A method of manufacturing a layer structure includes: forming a first layer over a substrate; planarizing the first layer to form a planarized surface of the...
US-9,929,110 Integrated circuit wave device and method
A method of forming, and a resulting, an integrated circuit wave device. The method (i) affixes an integrated circuit die relative to a substrate; (ii) creates...
US-9,929,109 Stacking of multiple dies for forming three dimensional integrated circuit (3DIC) structure
Some embodiments of the present disclosure relate to a three dimensional integrated circuit (3DIC) structure. The 3DIC structure has a first die and a second...
US-9,929,108 Backside redistribution layer (RDL) structure
An embodiment package on package (PoP) device includes a molding compound having a metal via embedded therein, a passivation layer disposed over the molding...
US-9,929,107 Method for manufacturing a semiconductor device
In an embodiment, a method includes forming an opening in a front surface of a substrate including at least one Group III nitride-based transistor on the first...
US-9,929,106 Display device and active element substrate
A display device is provided. The display device includes a first substrate, a second substrate, a display layer, an active element layer, and a planar layer...
US-9,929,105 Leakage laser beam detecting method
A leakage laser beam detecting method includes a coating step of coating the lower surface of a wafer with an oil marker, thereafter, a press-bonding step of...
US-9,929,104 Semiconductor device including an optical measurement pattern
A semiconductor device includes a substrate including at least two semiconductor chip regions and a scribe lane region disposed between the semiconductor chip...
US-9,929,103 Misalignment checking device and manufacturing method of semiconductor device
According to one embodiment, an optical element branches reflection light from a first mark and a second mark having different focus positions, a first imaging...
US-9,929,102 Fan-out semiconductor package
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an...
US-9,929,101 Electronic assembly comprising a carrier structure made from a printed circuit board
An electronic assembly includes (a) a base carrier structure having a cavity formed therein, (b) a cover carrier structure, and (c) an electronic component...
US-9,929,100 Electronic component package and method of manufacturing the same
An electronic component package and a method of manufacturing an electronic component package are provided. An electronic component package includes a frame...
US-9,929,099 Planarized interlayer dielectric with air gap isolation
A semiconductor device includes an interlayer insulating layer including a first insulating layer on a substrate, and a plurality of interconnections in the...
US-9,929,098 Copper via with barrier layer and cap layer
A semiconductor device includes an insulating interlayer on a first region of a substrate. The insulating interlayer has a recess therein and includes a low-k...
US-9,929,097 Mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers
In some embodiments, an improved mechanical adhesion of copper metallization to dielectric with partially cured epoxy fillers is presented. In this regard, a...
US-9,929,096 Method for capping Cu layer using graphene in semiconductor
An interconnect structure includes a substrate, a dielectric layer on the substrate, a metal interconnect layer in the dielectric layer and in contact with the...
US-9,929,095 IO power bus mesh structure design
A MOS device includes an IO pad ring. The MOS device includes a first IO pad located on a first side of the IO pad ring, and a second IO pad located on a second...
US-9,929,094 Semiconductor device having air gap structures and method of fabricating thereof
A device including a first conductive feature and a second conductive feature having a coplanar top surface where the conductive features are disposed a first...
US-9,929,093 Semiconductor device and manufacturing method thereof
A semiconductor device includes a substrate including a cell area, a first contact area, and a second contact area; a lower stacked structure extending over the...
US-9,929,092 Treating copper interconnects
Techniques relate to treating metallic interconnects of semiconductors. A metallic interconnect is formed in a layer. A metallic cap is disposed on top of the...
US-9,929,091 Vertical fuse structures
Semiconductor devices and methods are provided in which vertical fuse devices are integrally formed with FINFET (Fin Field Effect Transistor) devices, wherein...
US-9,929,090 Antifuse element using spacer breakdown
Techniques and circuitry are disclosed for efficiently implementing programmable memory array circuit architectures, including both non-volatile and volatile...
US-9,929,089 Inductive connection structure for use in an integrated circuit
An embodiment in a single structure combines a pad comprising a connection terminal suitable for coupling the circuit elements integrated in a chip to circuits...
US-9,929,088 Airgap protection layer for via alignment
A method for via alignment includes forming first airgaps between interconnect structures and depositing a pinch off layer to close off openings to the first...
US-9,929,087 Enhancing integrated circuit density with active atomic reservoir
An integrated circuit (IC) comprises first and second conductors in one layer of the IC, wherein the first conductor is oriented along a first direction, the...
US-9,929,086 Semiconductor device
In a semiconductor device (SD), plate-shaped upper electrodes (UEL) are formed on a lower electrode (LEL) with a dielectric film (DEC) interposed therebetween....
US-9,929,085 Integrated circuit structure having deep trench capacitor and through-silicon via and method of forming same
One aspect of the disclosure relates to an interposer. The interposer may include: a first dielectric layer extending from a substrate in a direction away from...
US-9,929,084 Device with interconnection structure for forming a conduction path or a conducting plane with high decoupling...
Electronic device comprising an interconnection structure comprising an alternating stack of arrays of conducting lines and dielectric layers in which: all...
US-9,929,083 Semiconductor packages and package modules using the same
A semiconductor package includes a flexible film substrate including a chip mounting region and a cut-line interposed between an inner region and an outer...
US-9,929,082 Receiving structure for electrically connecting a nano-object on a surface thereof and re-establish electrical...
Receiving structure for electrically connecting a nano-object on a surface thereof and re-establish electrical contact with the nano-object on the opposite...
US-9,929,081 Interposer fabricating process
An interposer fabricating process includes the following steps. A substrate, an oxide layer, and a dielectric layer are stacked from bottom to top, and an...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.