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Patent # Description
US-9,929,080 Forming a stress compensation layer and structures formed thereby
Methods of forming a microelectronic structure are described. Those methods comprise forming a stress compensation layer on a substrate, forming at least one...
US-9,929,079 Leadless electronic packages for GAN devices
Leadless electronic packages for GaN-based half bridge power conversion circuits have low inductance internal and external connections, high thermal...
US-9,929,078 Semiconductor package structure and method for manufacturing the same
A semiconductor package structure includes a conductive structure, at least two semiconductor elements and an encapsulant. The conductive structure has a first...
US-9,929,077 Magnetic sensor
A magnetic sensor includes a semiconductor element, a lead frame, a bonding wire, and a package. The lead frame includes a die pad to which the semiconductor...
US-9,929,076 Semiconductor package of a flipped MOSFET chip and a multi-based die paddle with top surface groove-divided...
The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a...
US-9,929,075 Chip-scale electronic package structure with conductive connective element having increased surface area and...
An electronic package includes a lead frame structure having one or more structural features configured to improve board level reliability. In one embodiment,...
US-9,929,074 Highly oriented graphite
Use of highly oriented graphite including graphite layers placed on top of one another and containing only a small amount of water allows for production of an...
US-9,929,073 Semiconductor device
A semiconductor device includes: a first power semiconductor element; a second power semiconductor element that is connected in parallel with the first power...
US-9,929,072 Packaged semiconductor devices
A semiconductor device has a semiconductor chip having a first surface with metallized terminals and a parallel second surface. A frame of insulating material...
US-9,929,071 Dicing in wafer level package
A package includes a device die, and an encapsulating material encircling the device die. The encapsulating material includes a first portion with a...
US-9,929,070 Isolation rings for packages and the method of forming the same
A device includes a first package component, and a second package component underlying, and bonded to, the first package component. A molding material is...
US-9,929,069 Semiconductor device and manufacturing method thereof
A method of manufacturing a semiconductor device includes providing a semiconductor substrate including a conductive pad disposed thereon; disposing a polymeric...
US-9,929,068 Film-like wafer mold material, molded wafer, and semiconductor device
A film-like wafer mold material for molding a wafer in a lump, the material including a multilayer structure constituted of at least a first film layer and a...
US-9,929,067 Ceramic package, method of manufacturing the same, electronic component, and module
A method of manufacturing a ceramic package is provided. An electrically conductive paste is applied to an inside of the first hole and an inside of the second...
US-9,929,066 Power semiconductor device module baseplate having peripheral heels
The baseplate of a power semiconductor device module makes reliable and superior thermal contact with a heatsink when fixed to the heatsink. The baseplate...
US-9,929,065 Low-cost packaging for fluidic and device co-integration
The present disclosure provides methods for packaging a chip and packaged chips in which the chip and packaging are co-planar and gap-less. In certain...
US-9,929,064 Through-substrate via (TSV) testing
Various embodiments comprise apparatuses and methods for testing and repairing through-substrate vias in a stack of interconnected dice. In various embodiments,...
US-9,929,063 Process for making an integrated circuit that includes NCEM-Enabled, tip-to-side gap-configured fill cells,...
A process for making an integrated circuit, either in the form of a wafer, die, or chip, includes instantiating multiple standard cell-compatible fill cells,...
US-9,929,062 Abnormality portent detection system and method of manufacturing semiconductor device
According to one embodiment, in an abnormality portent detection system, a collection unit time-sequentially collects plural kinds of parameters related to a...
US-9,929,061 Mounting apparatus
A mounting apparatus is provided which includes a frame having a table, a support member disposed on the table to support a substrate, and a feeder mounted on a...
US-9,929,060 Porous silicon relaxation medium for dislocation free CMOS devices
A method for forming CMOS devices includes masking a first portion of a tensile-strained silicon layer of a SOI substrate, doping a second portion of the layer...
US-9,929,059 Dual liner silicide
A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate...
US-9,929,058 Vertical FETS with variable bottom spacer recess
A method of forming a variable spacer in a vertical transistor device includes forming a first source/drain of a first transistor on a substrate; forming a...
US-9,929,057 HDP fill with reduced void formation and spacer damage
A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first...
US-9,929,056 Method for forming gate structures in different operation voltages
A method for forming gate structures for a HV device and a MV device is provided. The method includes forming a HV oxide layer on the substrate, covering a...
US-9,929,055 Method to grow thin epitaxial films at low temperature
Implementations of the present disclosure generally relate to methods for epitaxial growth of a silicon material on an epitaxial film. In one implementation,...
US-9,929,054 Systems and methods for laser splitting and device layer transfer
Methods and systems are provided for the split and separation of a layer of desired thickness of crystalline semiconductor material containing optical,...
US-9,929,053 Systems and methods for controlling release of transferable semiconductor structures
The disclosed technology relates generally to methods and systems for controlling the release of micro devices. Prior to transferring micro devices to a...
US-9,929,052 Wafer processing method
A wafer is processed by transferring a wafer to a holding surface of a chuck table by using a suction pad. The front side of the wafer is held through a...
US-9,929,051 Wafer dicing method
A wafer dicing method comprises providing a wafer and performing a cutting procedure and a contacting procedure. The wafer includes a plurality of dies and a...
US-9,929,050 Mechanisms for forming three-dimensional integrated circuit (3DIC) stacking structure
Embodiments of mechanisms of forming a semiconductor device are provided. The semiconductor device includes a first semiconductor wafer comprising a first...
US-9,929,049 Gate tie-down enablement with inner spacer
A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner...
US-9,929,048 Middle of the line (MOL) contacts with two-dimensional self-alignment
Disclosed are methods of forming an integrated circuit (IC) structure with self-aligned middle of the line (MOL) contacts and the resulting IC structure. In the...
US-9,929,047 Partial spacer for increasing self aligned contact process margins
A semiconductor structure is provided. The semiconductor includes a gate stack on a substrate. The semiconductor includes a first set of sidewall spacers on...
US-9,929,046 Self-aligned contact cap
A method for forming a semiconductor device includes recessing a gate conductor in a gate structure to form a first divot, forming a gate cap in the first divot...
US-9,929,045 Defect inspection and repairing method and associated system and non-transitory computer readable medium
A defect inspection and repairing method is disclosed. The method includes: providing a wafer including a semiconductor chip disposed on a surface of the wafer;...
US-9,929,044 Method of manufacturing semiconductor device
To provide a semiconductor device with low parasitic capacitance, a semiconductor device with low power consumption, a semiconductor device having favorable...
US-9,929,043 Semiconductor memory device and method for manufacturing the same
A semiconductor memory device according to an embodiment includes: a pair of insulating members separated from each other, the pair of insulating members...
US-9,929,042 Semiconductor device having a discontinued part between a first insulating film and a second insulating film
A semiconductor device, in which an increase in the size of a product can be suppressed and a withstand voltage between wiring layers can be improved, and a...
US-9,929,041 Semiconductor device and method for manufacturing same
According to one embodiment, a semiconductor device includes a foundation layer, a stacked body, and an insulating layer. The stacked body provides on the...
US-9,929,040 Process for fabricating a structure having a buried dielectric layer of uniform thickness
A process is used for fabricating a final structure comprising in succession a useful semiconductor layer, a dielectric layer and a carrier substrate. The...
US-9,929,039 Method for manufacture of a semiconductor wafer suitable for the manufacture of an SOI substrate, and SOI...
A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a...
US-9,929,038 Insulating structure, a method of forming an insulating structure, and a chip scale isolator including such an...
A method of forming an insulating structure, comprising forming an insulating region comprising at least one electrical or electronic component or part thereof...
US-9,929,037 Sol gel coated support ring
A support member for a thermal processing chamber is described. The support member has a sol coating on at least one surface. The sol coating contains a...
US-9,929,035 Method of producing a removable wafer connection and carrier for wafer support
A relief structure is formed on a surface of a carrier provided for accommodating a wafer, which is fastened to the carrier by a removable adhesive contacting...
US-9,929,034 Substrate transfer device
A substrate transfer device includes a casing and a substrate conveying robot. A size of the casing in a second direction Y is more than a size of the casing in...
US-9,929,033 Gas purge apparatus, load port apparatus, installation stand for purging container, and gas purge method
In a gas purge apparatus, a load port apparatus, an installation stand for a purging container, and a gas purge method, the inside of the purging container can...
US-9,929,032 Front opening wafer container with robotic flange
A front opening wafer container suitable, for large diameter wafers, 300 mm and above, utilizes a removable robotic flange that attaches vertically, without...
US-9,929,031 Methods and devices for securing and transporting singulated die in high volume manufacturing
A method includes identifying a wafer position for a plurality of die on a wafer, storing the wafer position for each of the plurality of die in a database,...
US-9,929,030 Substrate processing device and substrate transfer method
Provided is a substrate processing device capable of improving throughput without increasing the operation speed of a drive device. Vacuum processing chambers...
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