Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-9,928,218 Electronic text display upon changing a device orientation
Information is presented to a user by accessing a library of electronic publications that includes a first publication, generating a representation of the first...
US-9,928,217 Efficient handling of bi-directional data
A tool for standardized layout transformations of BIDI data exchanged between legacy and modern systems is provided. The tool retrieves client connection...
US-9,928,215 Iterative simple linear regression coefficient calculation for streamed data using components
Methods, systems, and computing system program products for iteratively calculating Simple Linear Regression (SLR) coefficients for streamed data, including...
US-9,928,214 Sketching structured matrices in nonlinear regression problems
A system, method and computer program product for quickly and approximately solving structured regression problems. In one aspect, the system, method and...
US-9,928,213 Event-driven spatio-temporal short-time fourier transform processing for asynchronous pulse-modulated sampled...
A method of processing asynchronous event-driven input samples of a continuous time signal includes calculating a short-time Fourier transform (STFT) output...
US-9,928,212 Subspace-constrained partial update method for high-dimensional adaptive processing systems
A method is explained for any adaptive processor processing digital signals by adjusting signal weights on digital signal(s) it handles, to optimize adaptation...
US-9,928,211 Parallel self-timed adder (PASTA)
A parallel self-timed adder (PASTA) is disclosed. It is based on recursive formulation and uses only half adders for performing multi-bit binary addition....
US-9,928,210 Constrained backup image defragmentation optimization within deduplication system
The present disclosure provides for defragmenting deduplicated data, such as one or more backup image files, stored in a deduplicated data store. A ...
US-9,928,209 Pre-buffering of content data items to be rendered at a mobile terminal
The present invention relates to methods and devices for pre-buffering one or more content data items to be rendered at a mobile terminal. In a first aspect of...
US-9,928,208 Methods to send extra information in-band on inter-integrated circuit (I2C) bus
System, methods and apparatus are described that offer improved performance of an Inter-Integrated Circuit (I2C) bus. Primary data may be encoded in first...
US-9,928,207 Generating transactions with a configurable port
Provided are systems and methods for generating transactions with a configurable port. In some implementations, a peripheral device is provided. The peripheral...
US-9,928,206 Dedicated LAN interface per IPMI instance on a multiple baseboard management controller (BMC) system with...
A system includes a management controller for managing a plurality of computing platforms. The management controller includes a processor, a physical network...
US-9,928,205 Semiconductor apparatus
A semiconductor apparatus may include a master chip, first to n.sup.th slave chips, first to n.sup.th slave chip ID generating units, and a master chip ID...
US-9,928,204 Transaction expansion for NoC simulation and NoC design
Methods and example implementations described herein are generally directed to interconnect architecture, and more specifically, to generation of one or more...
US-9,928,203 Object storage monitoring
Systems and methods are disclosed for monitoring object storage in a data storage system. A storage device tray assembly includes a plurality of data storage...
US-9,928,202 Time-division multiplexing data bus
A two-to-one multiplexor comprises a first data input configured to hold data provided from a first preceding asynchronous pipeline stage and a second data...
US-9,928,199 Low power software defined radio (SDR)
A communication apparatus comprising a plurality of signal processing units configured to perform a set of pre-determined signal processing functions according...
US-9,928,197 USB device and method thereof for recognizing host operating system
Provided are a USB device and a method thereof for recognizing a host operating system. The method comprises the following steps: a USB device waiting for...
US-9,928,196 Programming interface operations in a driver in communication with a port for reinitialization of storage...
A driver of a host bus adapter of a storage controller performs hardware resets of buses and other logic to which an embedded port of the host bus adapter is...
US-9,928,195 Interconnect and method of operation of an interconnect for ordered write observation (OWO)
An interconnect, and method of operation of an interconnect, are provided for connecting a plurality of master devices and a plurality of slave devices. Hazard...
US-9,928,194 Non-linear transmit biasing for a serial bus transmitter
Described embodiments provide a transmitter for transmitting data over a serial bus coupled to the transmitter. The transmitter includes a controller to...
US-9,928,193 Distributed timer subsystem
A silicon device configured to distribute a global timer value over a single serial bus to a plurality of processing elements that are disposed on the silicon...
US-9,928,192 Network controller--sideband interface port controller
A network interface controller includes a media access controller and a host adapter. The host adapter includes a transmit route connected to receive an in-band...
US-9,928,191 Communication device with selective encoding
A communication device includes a data source that generates data for transmission over a bus, and that further includes a data encoder coupled to receive and...
US-9,928,190 High bandwidth low latency data exchange between processing elements
Direct communication of data between processing elements is provided. An aspect includes sending, by a first processing element, data over an inter-processing...
US-9,928,189 Systems and methods for controlling devices using master and slave devices
A method and system for communicating, comprising: at least one master device comprising at least one master driver with at least one intelligent vending...
US-9,928,188 Battery pack to regulate access to media systems
Disclosed are devices which regulate the access to media systems such as console gaming systems by means of disconnecting the human interface device such as a...
US-9,928,187 Increasing data throughput in the image processing path of a document reproduction device
What is disclosed is a system and method for increasing throughput in the image processing path of a digital document reproduction device. A digital image to be...
US-9,928,186 Flash-DRAM hybrid memory module
A memory module that is couplable to a memory controller hub (MCH) of a host system includes a non-volatile memory subsystem, a data manager coupled to the...
US-9,928,185 Information processing apparatus and computer-readable recording medium having program recorded therein
Processing performance of inter-virtual OS communication is improved by including a first storage processing unit that stores shared data in a data sharing area...
US-9,928,184 Microcomputer
A microcomputer is provided for each of industrial apparatuses to synchronously control them and includes a CPU, a peripheral module, and a communication...
US-9,928,183 Priority framework for a computing device
Proving for a framework for propagating priorities to a memory subsystem in a computing system environment is disclosed herein. By way of example, a memory...
US-9,928,182 Direct interface between SRAM and non-volatile memory providing space efficiency by matching pitch in both memories
A memory system comprises an SRAM array and a NVM array. The SRAM array and NVM array are both organized in rows and columns. The NVM array is directly coupled...
US-9,928,181 Systems and methods for protection of reflective memory systems
A computing device within a reflective memory system includes a memory block and a special purpose processor. The memory block includes a plurality of memory...
US-9,928,180 Synchronizing a translation lookaside buffer with page tables
The translation lookaside buffer (TLB) of a processor is kept in synchronization with a guest page table by use of an indicator referred to as a "T" bit. The T...
US-9,928,179 Cache replacement policy
Cache replacement policy. In accordance with a first embodiment of the present invention, an apparatus comprises a queue memory structure configured to queue...
US-9,928,178 Memory-efficient management of computer network resources
Systems and methods are provided for managing a data store, invalidation requests, and/or resource requests. The system and methods may use one or more data...
US-9,928,177 Managing method for cache memory of solid state drive
A managing method for a cache memory of a solid state drive includes the following steps. When the solid state drive decides to perform a garbage collection, a...
US-9,928,176 Selecting cache transfer policy for prefetched data based on cache test regions
A processor applies a transfer policy to a portion of a cache based on access metrics for different test regions of the cache, wherein each test region applies...
US-9,928,175 Identification of a computing device accessing a shared memory
A method for identifying, in a system including two or more computing devices that are able to communicate with each other, with each computing device having...
US-9,928,174 Consistent caching
A consistent caching service for managing data consistency between a cache system and backing store is provided. The consistent caching service compares an...
US-9,928,173 Conditional inclusion of data in a transactional memory read set
Determining, by a processor having a cache, if data in the cache is to be monitored for cache coherency conflicts in a transactional memory (TM) environment. A...
US-9,928,172 Method and apparatus for accessing data stored in a storage system that includes both a final level of cache...
A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a...
US-9,928,171 Apparatuses and methods for providing data to a configurable storage area
Apparatuses and methods for providing data to a configurable storage area are disclosed herein. An example apparatus may include an extended address register...
US-9,928,170 Scatter/gather capable system coherent cache
In accordance with some embodiments, a scatter/gather memory approach may be enabled that is exposed or backed by system memory and uses conventional tags and...
US-9,928,169 Method and system for improving swap performance
A method and system for improving swap performance are provided. In one embodiment, a computing device is provided with a volatile memory and a non-volatile...
US-9,928,168 Non-volatile random access system memory with DRAM program caching
Systems, methods, and computer programs are disclosed for providing non-volatile system memory with volatile memory program caching. One such method comprises...
US-9,928,167 Information processing system and nonvolatile storage unit
According to one embodiment, a memory system includes a nonvolatile storage device and an information processing apparatus. The information processing apparatus...
US-9,928,166 Detecting hot spots through flash memory management table snapshots
Decisions about how to correlate logical address to physical addresses in a flash memory (or other non-volatile random access memory) is based at least in part...
US-9,928,165 Nonvolatile memory device and method of controlling suspension of command execution of the same
A nonvolatile memory device includes a memory cell array, a row decoder, a page buffer, and control logic. The memory cell array includes memory cells connected...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.