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Patent # Description
US-9,935,091 Package-on-package structures and methods for forming the same
A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further...
US-9,935,090 Substrate design for semiconductor packages and method of forming same
An embodiment device includes a first die, a first molding compound extending along sidewalls of the first die, and one or more first redistribution layers...
US-9,935,089 Packaging optoelectronic components and CMOS circuitry using silicon-on-insulator substrates for photonics...
Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For...
US-9,935,088 Packaging optoelectronic components and CMOS circuitry using silicon-on-insulator substrates for photonics...
Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For...
US-9,935,087 Three layer stack structure
Vertically stacked system in package structures are described. In an embodiment, a package includes a first level molding and fan out structure, a third level...
US-9,935,086 Package substrate and light emitting device package
Provided are a package substrate and a light emitting device package. The package substrate may include a base substrate having a plurality of mounting regions...
US-9,935,085 Semiconductor substrates with unitary vias and via terminals, and associated systems and methods
Semiconductor substrates with unitary vias and via terminals, and associated systems and methods are disclosed. A representative system in accordance with a...
US-9,935,084 Devices and methods of packaging semiconductor devices
Devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a device includes a first semiconductor device and a second...
US-9,935,083 Semiconductor package and manufacturing method thereof
A semiconductor package and a method of manufacturing a semiconductor package. As a non-limiting example, various aspects of this disclosure provide a...
US-9,935,082 Stacked semiconductor dies with selective capillary under fill
Stacked semiconductor dies are provided with selective capillary under fill to avoid wafer warpage during curing. In one embodiment, a method of manufacturing a...
US-9,935,081 Hybrid interconnect for chip stacking
Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes...
US-9,935,080 Three-layer Package-on-Package structure and method forming same
A method includes forming a first plurality of redistribution lines, forming a first metal post over and electrically connected to the first plurality of...
US-9,935,079 Laser sintered interconnections between die
Embodiments of a microelectronic packaged device and methods of making are provided, where the microelectronic packaged device includes a system package...
US-9,935,078 Bonding device
[Problem] To provide a bonding device in which a capillary can perform stable vibration from a low frequency to a high frequency while achieving lightening and...
US-9,935,077 Apparatus for eutectic bonding
An apparatus for eutectic bonding includes (a) a bonding frame that includes two substrates and (b) a frame device situated on the substrates, the frame device...
US-9,935,076 Structure and method for fabricating a computing system with an integrated voltage regulator module
Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated...
US-9,935,075 Wire bonding method and apparatus for electromagnetic interference shielding
Apparatuses relating generally to a microelectronic package having protection from electromagnetic interference are disclosed. In an apparatus thereof, a...
US-9,935,074 Semiconductor device and method for manufacturing same
A lead frame has a first sink, an island, and a control terminal. The lead frame is bent, and at a rear surface, the island is positioned closer to one surface...
US-9,935,073 Semiconductor structure and manufacturing method of the same
The present disclosure provides a semiconductor package, including a semiconductor die and a substrate having a first surface electrically coupled to the...
US-9,935,072 Semiconductor package and method for manufacturing the same
The present disclosure provides a semiconductor package that prevents a bump bridge from being formed between adjacent conductive bumps to realize a fine bump...
US-9,935,071 Semiconductor package with lateral bump structure
A semiconductor package includes a semiconductor device having an upper surface and a side, wherein the upper surface and the side form a corner of the...
US-9,935,070 Interconnect structures and methods of forming same
Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure...
US-9,935,069 Reducing solder pad topology differences by planarization
A technique is disclosed for causing the top surfaces of solder bumps on a chip to be in the same plane to ensure a more reliable bond between the chip and a...
US-9,935,068 Fan-out semiconductor package
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an...
US-9,935,067 Methods of forming connector pad structures, interconnect structures, and structures thereof
Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector...
US-9,935,066 Semiconductor package having a substrate structure with selective surface finishes
The present disclosure relates to a semiconductor package having a substrate structure with selective surface finishes, and a process for making the same. The...
US-9,935,065 Radio frequency device packages and methods of formation thereof
A semiconductor device package includes an integrated circuit chip comprising a radio frequency device. The radio frequency device includes active circuitry at...
US-9,935,064 Microelectronics package with inductive element and magnetically enhanced mold compound component
The present disclosure relates to a microelectronics package with an inductive element and a magnetically enhanced mold compound component, and a process for...
US-9,935,063 Rlink-on-die inductor structures to improve signaling
Integrated circuit (IC) chip "on-die" inductor structures (systems and methods for their manufacture) may improve signaling from a data signal circuit to a...
US-9,935,062 Backside fib probing detector in a forward and reverse body biasing architecture
An integrated circuit including a plurality of first semiconductor strips of a first conductivity type and of second semiconductor strips of a second...
US-9,935,061 Resin interposer, semiconductor device using resin interposer, and method of producing resin interposer
A resin interposer having a semiconductor chip mounted thereon to couple the semiconductor chip to a printed circuit board, the resin interposer includes a...
US-9,935,060 Method for processing a wafer and wafer structure
A method for processing a wafer in accordance with various embodiments may include: removing wafer material from an inner portion of the wafer to form a...
US-9,935,059 Wafer structure, fabrication method, and spray apparatus
A wafer structure and a method for fabricating the wafer structure, and a spray apparatus are provided. An exemplary method for forming the wafer structure...
US-9,935,058 Shielded package assemblies with integrated capacitor
Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a...
US-9,935,057 Multiple driver pin integrated circuit structure
An integrated circuit (IC) structure includes a plurality of driver pins at a driver pin level and oriented in a driver pin direction. Each layer of a plurality...
US-9,935,056 Semiconductor chip, method of manufacturing the semiconductor chip, and semiconductor package and display...
A semiconductor chip having an improved structure without an investment in photolithography equipment, a method of manufacturing the semiconductor chip, and a...
US-9,935,055 Methods of manufacturing a semiconductor device by forming a separation trench
A method of manufacturing a semiconductor device includes forming a separation trench into a first main surface of a semiconductor substrate and removing...
US-9,935,054 Mark forming method, mark detecting method, and device manufacturing method
A mark forming method includes: exposing a wafer with a mask image to form first and second resist marks that have different shapes than one another based on a...
US-9,935,053 Electronic component integrated substrate
An electronic component integrated substrate includes a first substrate including a first pad, a first solder resist layer provided with a first open portion...
US-9,935,052 Power line layout in integrated circuits
Circuitry having power lines with comparable path resistances may include input-output blocks in an integrated circuit (IC) that are coupled to respective sets...
US-9,935,051 Multi-level metallization interconnect structure
A semiconductor structure is provided that includes a contact structure containing a gouged upper surface embedded in at least a middle-of-the-line (MOL)...
US-9,935,050 Multi-tier three-dimensional memory devices including vertically shared source lines and method of making thereof
A multi-tier memory device includes a first tier structure overlying a substrate and containing a first alternating stack of first insulating layers and first...
US-9,935,049 E-fuse structure of semiconductor device
Provided is an e-fuse structure of a semiconductor device having improved fusing performance so as to enable a program operation at a low voltage. The e-fuse...
US-9,935,048 Integrated circuit inductor
An inductive device is formed in a circuit structure that includes alternating conductive and insulating layers. The device includes, in a plurality of the...
US-9,935,047 Bonding structures and methods forming the same
A method includes forming a first dielectric layer over a conductive pad, forming a second dielectric layer over the first dielectric layer, and etching the...
US-9,935,046 Package device and manufacturing method thereof
A package device and a method for fabricating thereof are provided. The package device includes a substrate, a redistribution structure, a circuit board...
US-9,935,045 Semiconductor device and method of forming cantilevered protrusion on a semiconductor die
A semiconductor device has a first semiconductor die with a base material. A covering layer is formed over a surface of the base material. The covering layer...
US-9,935,043 Interconnection substrate and semiconductor package
An interconnection substrate includes a first insulating layer, and an interconnection structure formed on the first insulating layer, wherein the...
US-9,935,042 Semiconductor package, smart card and method for producing a semiconductor package
A semiconductor package includes a chip, a layer which is thermally coupled to the chip and which is formed from a material having a triggering temperature of...
US-9,935,041 Multi-chip module clips with connector bar
A clip tape includes connected clip sets; each includes a first clip and a second clip oriented in a same direction, connected by a connector bar. A first...
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