Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-9,935,040 Semiconductor module
A semiconductor module can be realized, which is formed by mounting an electronic component and a bus bar by solder on a lead frame including a plurality of...
US-9,935,039 Pre-molded integrated circuit packages
A leadframe with pre-molded cavities includes an outer frame and a plurality of units. Each unit includes a die pad and a plurality of leads. For each unit, a...
US-9,935,038 Semiconductor device packages and methods
Semiconductor devices packages and methods are disclosed. In one embodiment, a package for a semiconductor device includes a substrate and a contact pad...
US-9,935,037 Multi-stacked device having TSV structure
A multi-stacked device includes a lower device having a lower substrate, a first insulating layer on the lower substrate, and a through-silicon-via (TSV) pad on...
US-9,935,036 Package assembly with gathered insulated wires
Some embodiments of the present disclosure describe an integrated circuit (IC) package assembly having first, second, and third insulated wires wire bonded with...
US-9,935,035 Fluid cooled trace/via hybrid structure and method of manufacture
An interposer structure including a dielectric base material, and a metal based interconnect structure extending through the dielectric base material from a...
US-9,935,034 Semiconductor device and semiconductor module having cooling fins
A semiconductor module having a plurality of cooling fins and a fixing cooling fin longer than the plurality of cooling fins, the fixing cooling fin having a...
US-9,935,033 Heat sink coupling using flexible heat pipes for multi-surface components
An apparatus including a primary device and at least one secondary device coupled in a planar array to a substrate; a first heat exchanger disposed on the...
US-9,935,032 Power electronics arrangement and vehicle with said arrangement
A power electronics arrangement has a power semiconductor module, with a contact spring, with a load connecting element and with a mounting device which is...
US-9,935,031 Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity...
A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed...
US-9,935,030 Resin-encapsulated semiconductor device
A first resin encapsulated body and a second resin encapsulated body are stacked to form a resin-encapsulated semiconductor device. The first resin encapsulated...
US-9,935,029 Printed wiring board for package-on-package
A printed wiring board for package-on-package includes a first insulating layer, a wiring layer including a conductor pattern and formed on first surface of the...
US-9,935,028 Method and apparatus for printing integrated circuit bond connections
A method for assembling a packaged integrated circuit is provided. The method includes placing a die into a cavity of a package base, securing the die to the...
US-9,935,027 Electronic device including a metal substrate and a semiconductor module embedded in a laminate
An electronic device having a substrate including a metal layer, an electrically insulating layer disposed above the substrate, a semiconductor module disposed...
US-9,935,026 Air-cavity package with dual signal-transition sides
The present disclosure relates to an air-cavity package, which includes a bottom substrate, a top substrate, a perimeter wall, a bottom electronic component,...
US-9,935,025 Electronic component housing package and electronic device
An electronic component housing package includes a substrate having an upper surface including a mount region on which an electronic component is to be mounted;...
US-9,935,024 Method for forming semiconductor structure
A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad...
US-9,935,023 Methods for manufacturing semiconductor device and for detecting end point of dry etching
A via hole is accurately formed in an interlayer insulating film over a metal wiring. Of emission spectra of plasma to be used for dry etching of the interlayer...
US-9,935,022 Systems and methods of characterizing process-induced wafer shape for process control using CGS interferometry
Systems and methods of characterizing wafer shape using coherent gradient sensing (CGS) interferometry are disclosed. The method includes measuring at least...
US-9,935,021 Method for evaluating a semiconductor wafer
A method for evaluating a semiconductor wafer including preparing a reference wafer in which contamination element and amount of contamination are known,...
US-9,935,020 Method of evaluating metal contamination in boron-doped P-type silicon wafer, device of evaluating metal...
An aspect of the present invention relates to a method of evaluating metal contamination in a boron-doped p-type silicon wafer, which comprises measuring over...
US-9,935,019 Method of fabricating a transistor channel structure with uniaxial strain
Method for creation of stressed channel structure transistors wherein at least one amorphizing ion implantation of the surface layer of a substrate of the...
US-9,935,018 Methods of forming vertical transistor devices with different effective gate lengths
One illustrative method disclosed herein includes, among other things, forming first and second vertically-oriented channel (VOC) semiconductor structures for,...
US-9,935,017 Methods of manufacturing semiconductor devices by forming source/drain regions before gate electrode separation
Spaced apart first and second fins are formed on a substrate. An isolation layer is formed on the substrate between the first and second fins. A gate electrode...
US-9,935,016 Silicon and silicon germanium nanowire formation
Among other things, one or semiconductor arrangements, and techniques for forming such semiconductor arrangements are provided. For example, one or more silicon...
US-9,935,015 Hybridization fin reveal for uniform fin reveal depth across different fin pitches
A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer...
US-9,935,014 Nanosheet transistors having different gate dielectric thicknesses on the same chip
Embodiments are directed to a method and resulting structures for forming thin and thick gate dielectric nanosheet transistors on the same chip. A first...
US-9,935,013 Flexible device modulation by oxide isolation structure selective etching process
A semiconductor device with an increased effective gate length or an increased effective channel width, and a method of forming the same are provided. The...
US-9,935,012 Methods for forming different shapes in different regions of the same layer
Disclosed are methods of forming different shapes in different regions of a specific layer. In the methods, a first mask layer and an etch process are used to...
US-9,935,011 Fin spacer protected source and drain regions in FinFETs
A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also...
US-9,935,010 Method of processing a wafer and wafer processing system
A wafer has a device area on one side with a plurality of devices partitioned by a plurality of division lines. Either side of the wafer is attached to an...
US-9,935,009 IR assisted fan-out wafer level packaging using silicon handler
A support structure for use in fan-out wafer level packaging is provided that includes, a silicon handler wafer having a first surface and a second surface...
US-9,935,008 Semiconductor device chip manufacturing method
Disclosed herein is a semiconductor device chip manufacturing method including a chipping prevention layer forming step of forming a chipping prevention layer...
US-9,935,007 Electronic device and method for fabricating the same
A semiconductor device may include: a plurality of first contacts arranged at a predetermined distance in a first direction and a second direction crossing the...
US-9,935,006 Trench liner for removing impurities in a non-copper trench
The present disclosure involves a method of fabricating a semiconductor device in a semiconductor technology node that is 5-nanometer or smaller. An opening is...
US-9,935,005 Techniques for filling a structure using selective surface modification
A method of device processing. The method may include providing a cavity in a layer, directing energetic flux to a bottom surface of the cavity, performing an...
US-9,935,004 Process and chemistry of plating of through silicon vias
A method and apparatus for processing a silicon substrate are provided. In some implementations, the method comprises providing a silicon substrate having an...
US-9,935,003 HDP fill with reduced void formation and spacer damage
A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first...
US-9,935,002 Conformal low temperature hermetic dielectric diffusion barriers
Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a...
US-9,935,001 Methods of forming an integrated circuit chip having two types of memory cells
An integrated circuit chip includes a first type memory cell and a second type memory cell. The first type memory cell includes a first reference line landing...
US-9,935,000 Slit stress modulation in semiconductor substrates
A disclosed example to modulate slit stress in a semiconductor substrate includes controlling a first process to apply a first material to a semiconductor...
US-9,934,999 Shallow trench isolation trenches and methods for NAND memory
A NAND memory is provided that includes a memory cell region and a peripheral region. The peripheral region includes a shallow trench isolation trench disposed...
US-9,934,998 Semiconductor device and method of singulating thin semiconductor wafer on carrier along modified region within...
A semiconductor device comprises a carrier including an adhesive disposed over the carrier. The semiconductor device further comprises a semiconductor wafer...
US-9,934,997 Adhesive sheet and method of manufacturing electronic component
An adhesive sheet is provided that is capable of inhibiting scraping up of an adhesive in the dicing step, does not cause chip detachment during dicing...
US-9,934,996 Wafer processing bonding arrangement, wafer laminate, and thin wafer manufacturing method
A bonding arrangement comprising a silicone-base adhesive composition is suited for temporarily bonding a wafer to a support for wafer processing. The bonding...
US-9,934,995 Method for manufacturing a handle substrate for the temporary bonding of a substrate
This process includes steps: a) providing a carrier substrate including a receiving face; b) depositing a nonstick coating on the receiving face, the nonstick...
US-9,934,994 Linearly moving and rotating device switchable between linearly moving and rotating
The linearly moving and rotating device includes a support portion that supports an operated member integrally provided with the article support portion, for...
US-9,934,993 Article transport facility
A controller performs a stop control if a first detector detects that an article transport vehicle traveling in a first path entered a managed area, and a...
US-9,934,992 Chamber for degassing substrates
A heater or cooler chamber for a batch of more than one workpiece includes a heat storage block. In the block a multitude of pockets are provided, whereby each...
US-9,934,991 Method and apparatus for planarizing material layers
A processing chamber is disclosed for planarizing material layers (for example, polymer layers). An exemplary processing chamber includes a substrate table...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.