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Patent # Description
US-9,934,887 Umbilical
An umbilical for use in the offshore production of hydrocarbons comprising an assembly of functional elements at least one of which is an electrical power...
US-9,934,886 Stable and easy-to-install and remove multi-conductive core cable and processing method thereof
The present invention discloses a stable and easy-to-install and remove multi-conductive core cable, an outer protective layer and cable inner core wires...
US-9,934,885 Electrical Harness
A gas turbine engine 10 is provided with electrical harness rafts 200 comprising electrical conductors embedded in a rigid composite material. The rafts 200 are...
US-9,934,884 Connection plates for power feeding
Plural pairs of connection plates are placed circumferentially around a plurality of circularly-arranged electromagnets, in which the plural pairs are each a...
US-9,934,883 Halogen free flame retardant thermoplastic elastomer compositions having improved insulation resistance
Halogen-free flame retardant compositions comprising copolyetherester thermoplastic elastomers, melamine cyanurate and epoxy-containing compounds and cables and...
US-9,934,882 Amine compound and ionic conductive agent, and electroconductive resin composition
An amine compound and an ionic conductive agent excellent in electroconductivity are provided. By using the amine compound, an electroconductive resin...
US-9,934,881 Non-metallic light conductive wire and its method and application products
The present invention relates to a non-metallic light conductive wire, a composite conductive wire, a special cable, a motor and the like application products...
US-9,934,880 Copper paste composition and its use in a method for forming copper conductors on substrates
This invention relates to a copper thick film paste composition paste comprising copper powder, a Pb-free, Bi-free and Cd-free borosilicate glass frit,...
US-9,934,879 Fuel rod support insert for a nuclear fuel assembly spacer grid, spacer grid and nuclear fuel assembly
A fuel rod support insert for a nuclear fuel assembly spacer grid, a spacer grid and a nuclear fuel assembly are provided. The support insert is for a nuclear...
US-9,934,878 Spot welding gun and welding method for the nuclear fuel skeleton
A spot welding device for a nuclear fuel skeleton, which is assembled by spot-welding guide tubes for control rods and a instrumentation tube for measuring a...
US-9,934,877 Nanocrystalline/amorphous composite coating for protecting metal components in nuclear plants cooled with...
A nuclear fuel cladding tube for a liquid-metal or molten-salt cooled reactor includes a tubular body of metal material and a protective coating applied on an...
US-9,934,876 Magnetic field plasma confinement for compact fusion power
In one embodiment, a fusion reactor includes two internal magnetic coils suspended within an enclosure, a center magnetic coil coaxial with the two internal...
US-9,934,875 Integrated circuit and memory device performing boot-up operation
An integrated circuit may include nonvolatile memory suitable for outputting stored data during the boot-up operation, one or more registers suitable for...
US-9,934,874 Storage medium management device, storage medium management method, storage medium, and storage medium...
A storage medium management device may include a non-volatile storage, an error information register, and a congenital defective block identification register....
US-9,934,873 Delayed equivalence identification
A method includes configuring an integrated circuit comprising one or more registers to provide a free running clock in the integrated circuit, simulating N...
US-9,934,872 Erase stress and delta erase loop count methods for various fail modes in non-volatile memory
Techniques are presented for using erase stress and variations in the loop count (number of cycles) for various fail modes in non-volatile memories, including...
US-9,934,871 Verification of storage media upon deployment
Described here in are systems, methods and, software to verify storage media and storage subsystems upon deployment. In one example, a computer apparatus to...
US-9,934,870 Apparatuses and methods for memory testing and repair
Some embodiments include apparatuses and methods having a first interface to communicate with a processing unit, a second interface to communicate with a memory...
US-9,934,869 Apparatuses and methods for flexible fuse transmission
Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each...
US-9,934,867 Capacitance coupling parameter estimation in flash memories
A method for capacitance coupling parameter estimation is disclosed. Step (A) of the method determines a plurality of voltages in a plurality of memory cells of...
US-9,934,866 Memory device with defined programming transaction time
This disclosure provides a method of accurately determining expected transaction times associated with flash memory subdivisions, such as devices, blocks or...
US-9,934,865 Dynamically adjusting read voltage in a NAND flash memory
A NAND flash memory device detects the occurrence of Cell Voltage Distribution Disruption Events (CVDDEs), such as a Partial Block Program (PBP) and...
US-9,934,864 Method of setting a reference current in a nonvolatile memory device
A nonvolatile memory device comprises a cell array including a memory cell. The nonvolatile memory device also includes a reference signal generator configured...
US-9,934,863 Dynamically adjusting read voltage in a NAND flash memory
A NAND flash memory device detects the occurrence of Cell Voltage Distribution Disruption Events (CVDDEs), such as a Partial Block Program (PBP) and...
US-9,934,862 Rank determination
Technologies are generally provided for methods and circuitry to rank a large number of cells in a timeframe of about one sense cycle. In some examples, an...
US-9,934,861 Semiconductor memory device capable of reducing chip size
According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is...
US-9,934,860 Semiconductor memory device and method for driving same
A semiconductor memory device includes first to fourth electrodes; first and second semiconductor members; a first charge storage member provided between the...
US-9,934,859 Determining demarcation voltage via timestamps
In response to a write operation on a storage element in a non-volatile memory device, a count provided by a global counter is stored to indicate a time at...
US-9,934,858 Use of dummy word lines for metadata storage
In a non-volatile memories formed according to a NAND type of architecture, one or more of the end word lines on the source end, drain end, or both are set...
US-9,934,857 Ternary content addressable memories having a bit cell with memristors and serially connected match-line...
An example ternary content addressable memory. A bit cell of the memory may include a first memristor that has a first terminal that is connected to a first...
US-9,934,856 Apparatuses and methods for comparing data patterns in memory
Apparatuses and methods related to comparing data patterns in memory. An example method can include comparing a number of data patterns stored in a memory array...
US-9,934,855 Node retainer circuit incorporating RRAM
A retainer node circuit is provided that can retain state information of a volatile circuit element (e.g., a flip-flop, latch, switch, register, etc.) of an...
US-9,934,854 Memory controllers comparing a difference between measured voltages with a reference voltage difference
A memory controller includes a voltage driver and a voltage comparator. The voltage driver applies a variable voltage to a selected line of a crossbar array to...
US-9,934,853 Method and apparatus for reading RRAM cell
The present disclosure relates to a method and apparatus for performing a read operation of an RRAM cell, which applies a non-zero bias voltage to unselected...
US-9,934,852 Sensing an output signal in a crossbar array based on a time delay between arrival of a target output and a...
A method of sensing an output signal in a crossbar array is described. In the method, a selecting voltage is applied to a target memory element of the crossbar...
US-9,934,851 Resistance memory cell
A resistance memory includes a resistance memory cell having a resistance memory element and a two-terminal access device in series. The two-terminal access...
US-9,934,850 Accessing memory cells in parallel in a cross-point array
Methods and structures for accessing memory cells in parallel in a cross-point array include accessing in parallel a first memory cell disposed between a first...
US-9,934,849 Asymmetrically selecting memory elements
A system for asymmetrically selecting a memory element is described. The system includes a number of memory cells in a crossbar array. Each memory cell includes...
US-9,934,848 Methods for determining the resistive states of resistive change elements
Devices and methods for determining resistive states of resistive change elements in resistive change element arrays are disclosed. According to some aspects of...
US-9,934,847 Memory system storing 4-bit data in each memory cell and method of controlling thereof including soft bit...
According to one embodiment, a memory system acquires HB information and SB1 information through SB4 information on each of four pages including LOWER, MIDDLE,...
US-9,934,846 Memory circuit and method for increased write margin
A memory circuit includes a plurality of bit-cells organized in a column. Each bit-cell of the plurality is coupled to first and second voltage supply...
US-9,934,845 Latch with built-in level shifter
A semiconductor device comprising a first supply voltage, a second supply voltage, different from the first supply voltage; and a switching circuit. The...
US-9,934,844 SRAM bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual...
Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in...
US-9,934,843 SRAM cell with dynamic split ground and split wordline
An SRAM cell with dynamic split ground (GND) and split wordline (WL) for extreme scaling is disclosed. The memory cell includes a first access transistor...
US-9,934,842 Multiple rank high bandwidth memory
Methods and apparatus related to multiple rank high bandwidth memory are described. In one embodiment, a semiconductor package includes a high bandwidth memory...
US-9,934,841 Systems and methods for refreshing data in memory circuits
A memory refreshing circuit implemented on an integrated circuit comprising a memory circuit that stores original data and an algorithmic data generation...
US-9,934,840 Method and circuit enabling ferroelectric memory to be fixed to a stable state
A system includes a ferroelectric random access memory (FRAM) array having one or more memory elements. A cycle controller cycles data to be fixed in a subset...
US-9,934,839 Dynamic adjustment of memory cell digit line capacitance
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be used to store a logic state....
US-9,934,838 Pulse shaping unit cell and array for symmetric updating
A memory unit cell and memory array device are provided. The memory unit cell includes a pulse adjustment circuit for providing an adjusted pulse with symmetric...
US-9,934,837 Ground reference scheme for a memory cell
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line...
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