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Patent # Description
US-9,934,170 Circuit for controlling access to memory using arbiter
The present invention relates to a technology enabling a normal access by controlling a read access through an arbiter in a circuit for controlling an access to...
US-9,934,169 Operating method of input/output interface
A method of operating an input/output interface includes selecting one of a plurality of output driver circuits according to a mode selection signal, and...
US-9,934,168 Method and system of connecting and switching grouped input and output devices between computers
A system, method, and computer readable medium for switching (via a hub connection device) peripheral devices (such as a display, keyboard, mouse, audio)...
US-9,934,167 Method and control device for commissioning a sensor series circuit configured in a daisy chain topology,...
A method for commissioning a sensor series circuit configured in a daisy chain topology. A second sensor being downstream from a first sensor. The method...
US-9,934,166 Hard object: constraining control flow and providing lightweight kernel crossings
A method providing simple fine-grain hardware primitives with which software engineers can efficiently implement enforceable separation of programs into modules...
US-9,934,165 Apparatus for monitoring data access to internal memory device and internal memory device
The application discloses an apparatus for monitoring data access to internal memory device and an internal memory device. The internal memory device is coupled...
US-9,934,164 Memory write protection for memory corruption detection architectures
Memory corruption detection technologies are described. A system on a chip (SoC) may include a memory device and a memory controller. The memory device may...
US-9,934,163 Selectively delaying cache flushing to promote write efficiency
A technique for managing storage in a data storage system includes ingesting host data into a data log backed by pages in a cache. The host data are addressed...
US-9,934,161 Expiring virtual content from a cache in a virtual universe
Approaches for expiring cached virtual content in a virtual universe are provided. In one approach, there is an expiration tool, including an identification...
US-9,934,160 Bit-mapped DMA and IOC transfer with dependency table comprising plurality of index fields in the cache for DMA...
The invention provides the data flow communication control between the source (flash/IO) and destination (IO/flash) cores. The source and destination cores are...
US-9,934,159 Dynamic address translation with fetch protection in an emulated environment
What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated is first obtained and an initial...
US-9,934,158 System and methods exchanging data between processors through concurrent shared memory
A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a...
US-9,934,157 Post-copy VM migration speedup using free page hinting
A system and methods for migrating a virtual machine (VM). In one embodiment, a hypervisor receives a request to migrate the contents of a memory of a source VM...
US-9,934,156 Host traffic separation scheme for sudden power loss scenario
A host write is received which includes a write address and write data. It is determined if the write address is already stored in at least one of a plurality...
US-9,934,155 Method, system, and apparatus for page sizing extension
A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size,...
US-9,934,154 Electronic system with memory management mechanism and method of operation thereof
An electronic system includes: a processor configured to access operation data; a local cache memory, coupled to the processor, configured to store a limited...
US-9,934,153 Patch memory system
A patch memory system for accessing patches from a memory is disclosed. A patch is an abstraction that refers to a contiguous, array of data that is a subset of...
US-9,934,152 Method and apparatus to use hardware alias detection and management in a virtually indexed physically tagged cache
Systems and techniques relating to hardware alias detection and management in caches are described. A cache controller can receive a cache request that...
US-9,934,151 System and method for dynamic optimization for burst and sustained performance in solid state drives
A method and information handling system configured to executing instructions of an SSD dynamic optimization buffer switching system and configured to detecting...
US-9,934,149 Prefetch mechanism for servicing demand miss
Systems and methods relate to servicing a demand miss for a cache line in a first cache (e.g., an L1 cache) of a processing system, for example, when none of...
US-9,934,148 Memory module with embedded access metadata
A memory module stores memory access metadata reflecting information about memory accesses to the memory module. The memory access metadata can indicate the...
US-9,934,147 Content-aware storage tiering techniques within a job scheduling system
Techniques are provided for content-aware storage tiering techniques within a job scheduling system. A data node in a job scheduling environment receives at...
US-9,934,146 Hardware apparatuses and methods to control cache line coherency
Methods and apparatuses to control cache line coherency are described. A processor may include a first core having a cache to store a cache line, a second core...
US-9,934,145 Organizing memory to optimize memory accesses of compressed data
In one embodiment of the present invention a cache unit organizes data stored in an attached memory to optimize accesses to compressed data. In operation, the...
US-9,934,144 Cache allocation for disk array
A method for allocating cache for a disk array includes monitoring an I/O distribution of the disk array in a predetermined time period, determining a garbage...
US-9,934,143 Mapping a physical address differently to different memory devices in a group
A memory subsystem includes a group of memory devices connected to an address bus. The memory subsystem includes logic to uniquely map a physical address of a...
US-9,934,142 Wear leveling in a memory system
Embodiments are disclosed for replacing one or more pages of a memory to level wear on the memory. In one embodiment, a system includes a page fault handling...
US-9,934,141 System and method for efficiently managing a containment hierarchy
Systems and methods are provided for generating a user interface display on a graphical user interface. Native data is accessed from memory for generating a...
US-9,934,140 Allocating blocks in storage systems
A method is used in allocating blocks in storage systems. A block allocation request is received for a file of a file system. The block allocation request...
US-9,934,139 Virtualization in a multi-host environment
Methods and systems for implementing improved partitioning and virtualization in a multi-host environment are provided. According to one embodiment, multiple...
US-9,934,138 Application testing on a blockchain
A blockchain test configuration may provide a simple and secure infrastructure for testing applications. One example method of operation may comprise one or...
US-9,934,136 Automated generation of scripted and manual test cases
Systems and methods that provide manual test cases and scripted test cases automatically based on metadata included in a software application. In an embodiment,...
US-9,934,135 Generic test automation for application programming interface applications
A method for testing an application that invokes an application programming interface (API) comprises identifying signatures for APIs. A package associated with...
US-9,934,134 Generating a test scenario template from runs of test scenarios belonging to different organizations
System, method, and non-transitory computer-readable medium for generating a test scenario template from runs of test scenarios run on software systems...
US-9,934,133 Code coverage through overlay hooks
In an approach for utilizing overlay hooks to increase code coverage, a processor inserts an overlay hook in program code at a location within the program code...
US-9,934,131 Using model-based diagnosis to improve software testing
An artificial intelligence based method for improving a software testing process, according to which upon finding a bug, a set of candidate diagnoses is...
US-9,934,130 Software integration testing with unstructured database
According to examples, software integration testing with an unstructured database may include determining a driver class file for an integration testing tool to...
US-9,934,129 Determining application test results using screenshot metadata
A system generates screenshots of a graphical user interface (GUI) of an application that is displayed by target devices testing the application. Each...
US-9,934,128 Dynamic per-method probing during runtime
A system, method, and techniques for dynamically probing a method are provided. An example method includes identifying a target method to probe in an...
US-9,934,127 Indexing a trace by insertion of key frames for replay responsiveness
Inserting key frames during indexing of a trace for responsive trace replay. A method includes identifying responsiveness goal(s) for trace replay, including...
US-9,934,126 Indexing a trace by insertion of reverse lookup data structures
Augmenting a trace with at least one reverse lookup data structure during indexing of the trace. A method includes receiving trace data observed during...
US-9,934,125 Generation and display of in-line trace data after error detection
Techniques are described for providing error and trace data regarding execution of a computer program. A trace control parameter is disabled, and program...
US-9,934,124 Implementation of processor trace in a processor that supports binary translation
In an embodiment, a processor includes execution logic to execute binary translated (BT) code that is translated from native architecture (NA) code. The...
US-9,934,123 Targeted multi-tiered software stack serviceability
As disclosed herein a method, executed by a computer, for enabling multi-tiered software stack diagnostic collection includes initiating, on a first tier of a...
US-9,934,122 Extracting rich performance analysis from simple time measurements
Embodiments of the invention rely on simple time measurements to extract rich performance analysis from a graphics program. The invention times the program as...
US-9,934,121 Intent-based interaction with cluster resources
Aspects extend to methods, systems, and computer program products for intent-based interactions with cluster resources. One or more computer systems are joined...
US-9,934,120 Method and apparatus for updating a system on chip (SOC) image from a host computer system without using DMA
Embodiments of the present disclosure relate to systems and methods for updating a System on Chip (SOC) image without using direct memory access (DMA)...
US-9,934,119 Rogue hardware detection through power monitoring
Techniques are provided for monitoring power consumption for individual systems or devices as a way to detect illicit or rogue hardware, e.g., addition of an...
US-9,934,118 Reducing SPQL tester time for the critical paths stress test
Embodiments disclose techniques for executing a test case to test a processor by bypassing an instruction pipeline of the processor. In one embodiment, the...
US-9,934,117 Apparatus and method for fault detection to ensure device independence on a bus
A method includes transmitting a first value to a first slave device via a communication bus, where the first value is within a first range of values associated...
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