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Patent # Description
US-9,941,436 Dual geometry trough solar concentrator
The present invention is a trough shaped solar concentrator and collector having its focal area and receiver located inside the trough structure below the...
US-9,941,435 Photovoltaic module and laminate
A photovoltaic module is disclosed. The photovoltaic module has a first side directed toward the sun during normal operation and a second, lower side. The...
US-9,941,434 Photoelectric conversion device, solar cell and method for manufacturing photoelectric conversion device
A photoelectric conversion device of an embodiment has a substrate, a bottom electrode comprising an electrode layer on the substrate and an intermediate...
US-9,941,433 Composite quantum-dot materials for photonic detectors
A composite quantum-dot photodetector comprising a substrate with a colloidally deposited thin film structure forming a photosensitive region, the thin film...
US-9,941,432 Semiconductor devices, a fluid sensor and a method for forming a semiconductor device
A semiconductor device comprises a plurality of quantum structures comprising predominantly germanium. The plurality of quantum structures are formed on a first...
US-9,941,431 Photodiode having a superlattice structure
A photodiode includes a light absorbing layer including a first superlattice structure that includes first semiconductor layers and second semiconductor layers,...
US-9,941,430 Silicon-based quantum dot device
A silicon-based quantum dot device (1) is disclosed. The device comprises a substrate (8) and a layer (7) of silicon or silicon-germanium supported on the...
US-9,941,429 Photovoltaic element
According to the present invention there is provided a photovoltaic element, comprising a photovoltaic laminate; a structural substrate; wherein the...
US-9,941,428 Nano-electrode multi-well high-gain avalanche rushing photoconductor
Provided is a detector that includes a scintillator, a common electrode, a pixel electrode, and a plurality of insulating layers, with a plurality of...
US-9,941,427 Solar cell and method of fabricating the same
Provided is a solar cell and a method of fabricating the same. The solar cell according to an embodiment includes a supporting substrate; a transparent...
US-9,941,426 Methods to introduce sub-micrometer, symmetry-breaking surface corrugation to silicon substrates to increase...
Provided is a method for fabricating a nanopatterned surface. The method includes forming a mask on a substrate, patterning the substrate to include a plurality...
US-9,941,425 Photoactive devices and materials
Deposition processes are disclosed herein for depositing thin films comprising a dielectric transition metal compound phase and a conductive or semiconducting...
US-9,941,424 Solar cell
A solar cell according to the embodiment includes a substrate; a first electrode layer on a substrate; a light absorbing layer on the first electrode layer; a...
US-9,941,423 Method for manufacturing thin film solar cell
A method for manufacturing a thin film solar cell includes: depositing a transparent first rear electrode on a first surface of a transparent substrate;...
US-9,941,422 Organic photoelectric conversion element and solar cell using the same
Provided are a transparent conductive film having a simple manufacturing process and high transparency, high photoelectric conversion efficiency, and excellent...
US-9,941,421 Solar photovaltaic module rapid shutdown and safety system
A photovoltaic (PV) module safety shutdown system includes a module-on switch coupled with a PV module coupled with an alternating current (AC) mains panel...
US-9,941,420 Conductive paste, method for forming wiring, electronic component, and silicon solar cell
This conductive paste is such that the printing properties and sintering properties are superior and is formed such that resistance of wiring after sintering is...
US-9,941,419 Monolithically integrated thin-film device with a solar cell, an integrated battery, and a controller
A thin-film monolithically integrated solar module with a solar cell, an integrated energy storage device, and a controller may be provided. It may comprise a...
US-9,941,418 Schottky diode having a varied width structure
Provided herein is a Schottky diode including: a first semiconductor layer; an intermediate layer provided over the first semiconductor layer; a second...
US-9,941,416 MOS transistor and method of manufacturing the same
A MOS transistor includes a semiconductor layer resting on an insulator and having a substantially planar upper surface. The semiconductor layer extends down to...
US-9,941,415 Oxide sintered body, sputtering target, and oxide semiconductor thin film obtained using sputtering target
Provided are: a sintered oxide which achieves low carrier density and high carrier mobility when configured as an oxide semiconductor thin-film by using the...
US-9,941,414 Metal oxide semiconductor device
In a transistor including an oxide semiconductor film, a metal oxide film which has a function of preventing electrification and covers a source electrode and a...
US-9,941,413 Semiconductor device having different types of thin film transistors
It is an object to provide a semiconductor device having a new productive semiconductor material and a new structure. The semiconductor device includes a first...
US-9,941,412 Display device
According to one embodiment, a display device includes a first scanning line, a signal line, a second pixel electrode, a first pixel electrode, a second...
US-9,941,411 Vertical transistor fabrication and devices
A method of fabricating a vertical field effect transistor including forming a first recess in a substrate; epitaxially growing a first drain from the first...
US-9,941,410 Oxide thin film transistor and method of fabricating the same
The present disclosure relates to an oxide thin film transistor and a fabricating method thereof. In the oxide thin film transistor, which uses amorphous zinc...
US-9,941,409 Method for manufacturing a thin film transistor substrate
A thin film transistor substrate includes a semiconductor channel layer made of an oxide semiconductor, protective insulating layers that cover the...
US-9,941,407 Method of forming FinFET
A method of forming a FinFET is provided. A gate oxide layer and a dummy poly layer are substantially simultaneously etched using an etchant having a higher...
US-9,941,406 FinFETs with source/drain cladding
A device includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate. A semiconductor fin is between opposite portions...
US-9,941,405 Nanosheet and nanowire devices having source/drain stressors and methods of manufacturing the same
A method of manufacturing a nanosheet or nanowire device from a stack including an alternating arrangement of sacrificial layers and channel layers on a...
US-9,941,404 Tuning strain in semiconductor devices
A Fin Field-Effect Transistor (FinFET) includes a semiconductor layer over a substrate, wherein the semiconductor layer forms a channel of the FinFET. A first...
US-9,941,403 Semiconductor device and method for manufacturing a semiconductor device
A semiconductor device includes a transistor including a source region, a drain region, and a gate electrode. The gate electrode is disposed in a first trench...
US-9,941,402 Semiconductor devices and methods for forming a semiconductor device
A semiconductor device includes a guard structure located laterally between first and second active areas of a semiconductor substrate. The guard structure...
US-9,941,401 Semiconductor device, power supply apparatus and high-frequency amplifier
A semiconductor device includes a semiconductor stacked structure in which a semiconductor layer including an electron supply layer and an electron transit...
US-9,941,400 Semiconductor device and method of manufacturing the same
A semiconductor device includes: a substrate having a rear side on which a grounded electrode is disposed; a semiconductor layer disposed on a front side of the...
US-9,941,399 Enhancement mode III-N HEMTs
A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access...
US-9,941,398 High-electron-mobility transistor (HEMT) capable of protecting a III-V compound layer
A semiconductor structure comprises a semiconductive substrate comprising a top surface, a III-V compound layer over the semiconductive substrate, and a first...
US-9,941,397 Semiconductor device and method of manufacturing semiconductor device
In a trench deeper than a thickness of a p-type base layer and configured by a first trench and a second trench, a second trench positioned at a lower portion...
US-9,941,396 Semiconductor device and method of manufacturing same
To achieve a semiconductor device equipped with a low ON voltage and high load short circuit withstand trench gate IGBT. A collector region on a back surface of...
US-9,941,395 Insulated gate semiconductor device and method for manufacturing the same
An insulated gate semiconductor device includes a region that is provided between trenches in which a gate electrode is filled through a gate insulating film in...
US-9,941,394 Tunnel field-effect transistor
The tunnel field-effect transistor includes a drain layer, a source layer, a channel layer, a metal gate layer, and a high-k dielectric layer. The drain and...
US-9,941,393 Semiconductor device and method for manufacturing the same
A semiconductor device includes a substrate having an insulating surface; a light-transmitting first electrode provided over the substrate; a light-transmitting...
US-9,941,392 Gate planarity for FinFET using dummy polish stop
A method for forming a semiconductor device includes depositing a dielectric layer over fins formed in a semiconductor substrate. The dielectric layer includes...
US-9,941,391 Method of forming vertical transistor having dual bottom spacers
A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure on a substrate, depositing a first spacer on...
US-9,941,390 Method of fabricating a vertical MOS transistor
The disclosure relates to a method of fabricating a vertical MOS transistor, comprising the steps of: forming, above a semiconductor surface, a conductive layer...
US-9,941,389 Fabricating large area multi-tier nanostructures
Methods for fabricating and replicating self-aligned multi-tier nanoscale structures for a variety of cross-sectional geometries. These methods can utilize a...
US-9,941,388 Method and structure for protecting gates during epitaxial growth
Embodiments of the present invention provide methods and structures for protecting gates during epitaxial growth. An inner spacer of a first material is...
US-9,941,387 FinFET having a gate electrode with sidewall spacers having asymmetric dielectric constants and method of...
A semiconductor device may include the following elements: a fin member including a first doped portion, a second doped portion, and a semiconductor portion...
US-9,941,386 Semiconductor device structure with fin structure and method for forming the same
A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first fin...
US-9,941,385 Finfet with reduced capacitance
A structure including a gate electrode above and perpendicular to a plurality of semiconductor fins, a pair of spacers disposed on opposing sides of the gate...
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