Easy To Use Patents Search & Patent Lawyer Directory

At Patents you can conduct a Patent Search, File a Patent Application, find a Patent Attorney, or search available technology through our Patent Exchange. Patents are available using simple keyword or date criteria. If you are looking to hire a patent attorney, you've come to the right place. Protect your idea and hire a patent lawyer.

Searching:





Search by keyword, patent number, inventor, assignee, city or state:




Patent # Description
US-9,941,179 Capacitive measurements of divots in semiconductor devices
Approaches for characterizing a shallow trench isolation (STI) divot depth are provided. The approach includes measuring a first capacitance at a first region...
US-9,941,178 Methods for detecting endpoint for through-silicon via reveal applications
Systems and methods for processing a semiconductor wafer includes a plasma processing chamber. The plasma processing chamber includes an exterior, an interior...
US-9,941,177 Pattern accuracy detecting apparatus and processing system
A pattern accuracy detecting apparatus includes a stage for supporting a substrate, an optical warpage detecting unit that measures a shape of a substrate...
US-9,941,176 Selective solder bump formation on wafer
A method for selective bump formation on a wafer includes performing a wafer test on the wafer. Known good dies (KGDs) on the wafer are identified based on the...
US-9,941,175 Dielectric isolated SiGe fin on bulk substrate
A method for forming fins on a semiconductor device includes etching trenches into a monocrystalline substrate to form first fins and forming a first dielectric...
US-9,941,174 Semiconductor devices having fin active regions
Semiconductor devices are providing including a first isolation region configured to define a first fin active region protruding from a substrate, first gate...
US-9,941,173 Memory cell layout
A system and method for a memory cell layout is disclosed. An embodiment comprises forming dummy layers and spacers along the sidewalls of the dummy layer. Once...
US-9,941,172 Method for fabricating semiconductor device including a via hole in a mask pattern
A method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device includes forming an interlayer insulating layer...
US-9,941,171 Method for fabricating LDMOS with reduced source region
A method for fabricating a semiconductor device including: forming a block layer above a well region of a first doping type in a semiconductor substrate,...
US-9,941,170 PNP-type bipolar transistor manufacturing method
A PNP transistor is manufactured in parallel with the manufacture of NPN, NMOS, and PMOS transistors. A first semiconductor layer is deposited on a P-type doped...
US-9,941,169 Organic light emitting diode display device and method of fabricating the same
An organic light emitting diode display device comprises a driving thin film transistor including a first semiconductor layer, a gate insulating layer formed on...
US-9,941,168 Method for manufacturing semiconductor device by epitaxial lift-off using plane dependency of III-V compound
A method for manufacturing a semiconductor device by epitaxial lift-off includes: forming a sacrificial layer containing an III-V compound on a first substrate,...
US-9,941,167 Method for manufacturing element chip
The method includes a laser scribing step of forming an opening including an exposing portion, where the first layer is exposed, by irradiating the dividing...
US-9,941,166 Method of processing a substrate
The invention relates to a method of processing a substrate, having a first surface with a device area and a second surface opposite the first surface, wherein...
US-9,941,165 Semiconductor manufacturing method
A semiconductor manufacturing method includes forming a first metal film on a semiconductor wafer by plating, ejecting liquid from a washer bar spaced from the...
US-9,941,164 Self-aligned block patterning with density assist pattern
A method of generating mask layouts for self-aligned block patterning is provided. Metal line patterns to be formed on a semiconductor substrate is identified....
US-9,941,163 Gate tie-down enablement with inner spacer
A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner...
US-9,941,162 Self-aligned middle of the line (MOL) contacts
Disclosed are methods and integrated circuit (IC) structures. The methods enable formation of a gate contact on a gate above (or close thereto) an active region...
US-9,941,161 Method for fabricating semiconductor device
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon, a first...
US-9,941,160 Integrated circuits having device contacts and methods for fabricating the same
Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes...
US-9,941,159 Method of manufacturing a semiconductor device
A method of making a semiconductor device includes forming a first opening in an insulating layer, forming a second opening in the insulating layer, forming a...
US-9,941,158 Integrated circuit and process for fabricating thereof
A process for fabricating an Integrated Circuit (IC) and the IC formed thereby is disclosed. The process comprises providing a substrate. The process further...
US-9,941,157 Porogen bonded gap filling material in semiconductor manufacturing
A method for semiconductor manufacturing includes receiving a device that includes a substrate and a first layer disposed over the substrate, wherein the first...
US-9,941,156 Systems and methods to reduce parasitic capacitance
Devices and methods to reduce parasitic capacitance are disclosed. A device may include a dielectric layer. The device may include first and second conductive...
US-9,941,155 Methods for isolating portions of a loop of pitch-multiplied material and related structures
Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is...
US-9,941,154 Reverse self aligned double patterning process for back end of line fabrication of a semiconductor device
In a particular embodiment, a method includes forming a second hardmask layer adjacent to a first sidewall structure and adjacent to a mandrel of a...
US-9,941,153 Pad structure and manufacturing method thereof
A pad structure including a plurality of material pairs and a plurality of pads is provided. The material pairs are stacked on a substrate to form a stair step...
US-9,941,152 Mechanism for forming metal gate structure
Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a metal gate stack...
US-9,941,151 Method for producing an integrated circuit including a metallization layer comprising low K dielectric material
A method of forming a metallization layer of an IC having a lower via level and an upper trench level is disclosed. In one aspect, the method includes applying...
US-9,941,150 Method and structure for minimizing fin reveal variation in FinFET transistor
A method for manufacturing a semiconductor device includes forming a plurality of stacked portions spaced apart from each other on a substrate, each of the...
US-9,941,149 Receptacle device, device and method for handling substrate stacks
The invention relates to a retaining system for handling substrate stacks, including a retaining surface for retaining a first substrate, and one or more...
US-9,941,148 Wafer pin chuck fabrication and repair
In a wafer chuck design featuring pins or "mesas" making up the support surface, engineering the pins to have an annular shape, or to contain holes or pits,...
US-9,941,147 Transfer apparatus and laser annealing apparatus
A transfer apparatus includes a supporting member, a free electron excitation device and a detection device; the free electrons excitation device is configured...
US-9,941,146 Semiconductor device and method
Disclosed herein is a semiconductor device that includes a semiconductor die and a substrate having a first surface and a second surface. The semiconductor die...
US-9,941,145 Wafer processing temporary bonding arrangement, wafer processing laminate, and thin wafer manufacturing method
A temporary bonding arrangement for wafer processing is provided comprising a first temporary bond layer (A) of thermoplastic resin, a second temporary bond...
US-9,941,144 Substrate breakage detection in a thermal processing system
Apparatus, systems, and processes for substrate breakage detection in a thermal processing system are provided. In one example implementation, a process can...
US-9,941,143 Thin film transistor, display substrate having the same, and method of manufacturing the same
A thin film transistor include a control electrode, a semiconductor layer on the control electrode, an input electrode, at least a portion of the input...
US-9,941,142 Tunable TiOxNy hardmask for multilayer patterning
Lithographic multilayer structures are disclosed that generally include an organic planarizing layer and a tunable titanium oxynitride layer on the organic...
US-9,941,141 Guard ring structure of semiconductor arrangement
Among other things, one or more semiconductor arrangements and techniques for forming such semiconductor arrangements are provided. A semiconductor arrangement...
US-9,941,140 Semiconductor devices and methods of manufacture thereof
Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a semiconductor device includes a substrate, and a plurality of...
US-9,941,139 Method of semiconductor integrated circuit fabrication
A method of fabricating a semiconductor integrated circuit (IC) is disclosed. In one embodiment, a material layer is formed over a substrate and a first hard...
US-9,941,138 Method for exposing polysilicon gates
A method for exposing polysilicon gate electrodes is disclose. The method comprises planarizing a pre-metal dielectric on a wafer surface; performing a...
US-9,941,137 Substrate planarizing method and dropping amount calculating method
According to one embodiment, a substrate planarizing method includes dropping from above a substrate with topography, resist whose amount is determined in...
US-9,941,136 Back end of line (BEOL) method for polymer and biphenyl claddings
A method is provided for creating a chamber on a semiconductor substrate, utilizing wet etching or dry etching, back-filling the chamber with a polymeric...
US-9,941,135 Methods of forming a hard mask layer and of fabricating a semiconductor device using the same
A method of forming a hard mask layer on a substrate includes forming an amorphous carbon layer using nitrous oxide (N.sub.2O). A source of carbon and the...
US-9,941,134 Uniform dielectric recess depth during fin reveal
A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is...
US-9,941,133 Plasma processing apparatus and plasma processing method
A plasma processing apparatus includes a plasma processing chamber processing a sample using plasma, a radio frequency power supply supplying radio frequency...
US-9,941,132 Plasma processing apparatus and plasma processing method
A plasma processing apparatus includes: a reaction chamber; a plasma generation unit; a stage disposed inside the reaction chamber; an electrostatic chuck...
US-9,941,131 Method for applying developer on semiconductor wafer
A method for applying developer over a semiconductor wafer is provided. The method includes moving a nozzle over the center of the semiconductor wafer. The...
US-9,941,130 Thin plate separating method
A thin plate is separated from an SiC substrate having a first surface, an opposite second surface, a c-axis extending from the first surface to the second...
← Previous | 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 | Next →

File A Patent Application

  • Protect your idea -- Don't let someone else file first. Learn more.

  • 3 Easy Steps -- Complete Form, application Review, and File. See our process.

  • Attorney Review -- Have your application reviewed by a Patent Attorney. See what's included.