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Patent # Description
US-9,941,027 Process and installation for producing radioisotopes
The invention relates to a method for producing a radioisotope, which method comprises irradiating a volume of radioisotope-precursor fluid contained in a...
US-9,941,026 Glass composition for vitrifying low-level radioactive waste resin
This invention relates to the vitrification of radioactive waste products. According to this invention, a glass composition, which is suitable for low-level...
US-9,941,025 Nuclear fuel and method of fabricating the same
A nuclear fuel includes a volume of a nuclear fuel material defined by a surface, the nuclear fuel material including a plurality of grains, some of the...
US-9,941,024 Heating plasma for fusion power using electromagnetic waves
In one embodiment, a fusion reactor includes two internal magnetic coils suspended within an enclosure, a center magnetic coil coaxial with the two internal...
US-9,941,023 Post package repair (PPR) data in non-volatile memory
Example implementations relate to post package repair (PPR) data in non-volatile memory. In example implementations, PPR data may be stored in non-volatile...
US-9,941,022 Setting a default read signal based on error correction
A number of methods can include reading a page of data from a group of memory cells with a first discrete read signal and error correcting at least one codeword...
US-9,941,021 Plate defect mitigation techniques
Methods, systems, techniques, and devices for operating a ferroelectric memory cell or cells are described. Groups of cells may be operated in different ways...
US-9,941,020 Semiconductor system and method for testing semiconductor device
A semiconductor device includes a plurality of first input pins; a parity check unit suitable for performing a parity check for command/address signals inputted...
US-9,941,019 TFT-LCD, driving device and manufacturing method thereof
An embodiment of the disclosed technology provides a driving device for a thin film transistor liquid crystal display (TFT-LCD) and a method for manufacturing...
US-9,941,018 Gate driving circuit and display device using the same
A gate driving circuit and a display device using the same are discussed. The gate driving circuit according to an embodiment includes a first shift register...
US-9,941,017 Antifuse one-time programmable semiconductor memory
An antifuse one-time programmable (OTP) semiconductor memory comprises a PN junction diode formed in an active area of a semiconductor substrate proximate...
US-9,941,016 Flash memory device performing adaptive loop, memory system and method of operating the memory system
A method of operating a flash memory device includes detecting the number of program/erase cycles that have been executed by the flash memory device. A setting...
US-9,941,015 Semiconductor memory device
A semiconductor memory device includes first to third pages, first to the third word lines, and a row decoder. In data writing, data is written into the first...
US-9,941,014 Nonvolatile memory device, nonvolatile memory system including the same, and method of operating the same
A nonvolatile memory device includes a memory cell array having a normal area and a temporary area. A page buffer stores data to be written to the normal area...
US-9,941,013 Memory device that performs sensing operation during a bit line pre-charge operation to determine adjustment to...
A memory device includes memory cells, word lines that are each connected to gates of a plurality of the memory cells, bit lines that are each connected to a...
US-9,941,012 Twin memory cell interconnection structure
Non-volatile memory including rows and columns of memory cells, the columns of memory cells including pairs of twin memory cells including a common selection...
US-9,941,011 Memory array with one shared deep doped region
A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate...
US-9,941,010 Non-volatile memory with a variable polarity line decoder
The present disclosure relates to a memory including a memory array with at least two rows of memory cells, a first driver coupled to a control line of the...
US-9,941,009 Memory device having vertical structure and memory system including the same
A memory device has a vertical structure in which a row decoder, a page buffer, and a peripheral circuit are disposed under a memory cell array. The row decoder...
US-9,941,008 Ternary content addressable memory device for software defined networking and method thereof
The present disclosure illustrates a ternary content addressable memory (TCAM) device for software defined networking and method thereof. In the TCAM device, M...
US-9,941,007 Solid state drive architectures
A solid state drive includes DRAM logical flash and flash memory, in which system processor reads and writes only to the DRAM logical flash which minimizes...
US-9,941,006 Memory device and method for driving same
A memory device includes a first interconnect extending in a first direction, a second interconnect extending in a second direction crossing the first...
US-9,941,005 Fast read speed memory device
A memory cell includes a first resistive memory element, a second resistive memory element electrically coupled with the first resistive memory element at a...
US-9,941,004 Integrated arming switch and arming switch activation layer for secure memory
An arming switch structure and method of operation. The arming switch is integrated with a reactive material erasure device and phase change memory cell array...
US-9,941,003 Multi-level resistive memory structure
A resistive memory structure comprises a resistive memory element, a resistance block electrically connected to the memory element through an electrical node,...
US-9,941,002 Resistive memory and memory cell
A memory unit is provided. The memory unit includes a resistive element, a diode, and a first transistor. The resistive element has a first terminal receiving a...
US-9,941,001 Circuits for determining the resistive states of resistive change elements
Devices and methods for determining resistive states of resistive change elements in resistive change element arrays are disclosed. According to some aspects of...
US-9,941,000 Memory unit and method of operating a memory unit sector
Disclosed is a memory unit that includes a sector of memory cells. The sector includes a first memory cell configured to selectively take on a state...
US-9,940,999 Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on...
A method can of operating a semiconductor device can include generating a read or write assist signal having an enable logic level in response to a power supply...
US-9,940,998 Memory cell, memory device, and electronic device having the same
A memory device includes a memory cell array including a plurality of memory cells, a plurality of word lines connected to the plurality of memory cells, a...
US-9,940,997 Method and apparatus for enhancing read stability of a static random access memory circuit in low voltage operation
Read stability of a memory is enhanced in low voltage operation mode by selectively boosting a cell supply voltage for a row of memory cells. The boosted...
US-9,940,996 Memory circuit having increased write margin and method therefor
A memory circuit includes plurality of bit-cells organized in a column, each bit-cell of the plurality is coupled to a first voltage supply terminal and a...
US-9,940,995 Methods and apparatus for reusing lookup table random-access memory (LUTRAM) elements as configuration...
A programmable integrated circuit may include configuration random-access memory (CRAM) cells and lookup table random-access memory (LUTRAM) cells. The...
US-9,940,994 Write assist circuit for lowering a memory supply voltage and coupling a memory bit line
A circuit and method performs a write assist for a memory cell (e.g., a static random access memory cell (SRAM)). The method includes providing a lower supply...
US-9,940,992 Leakage-aware activation control of a delayed keeper circuit for a dynamic read operation in a memory bit cell
Leakage-aware activation control of a delayed keeper circuit for a dynamic read operation in a memory bit cell is disclosed. In one aspect, a leakage-aware...
US-9,940,991 Memory device and memory system performing request-based refresh, and operating method of the memory device
Provided are a memory device and a memory system performing request-based refresh, and an operating method of the memory device. The operating method includes:...
US-9,940,990 Data shift apparatuses and methods
The present disclosure includes data shift apparatuses and methods. An example apparatus includes a memory device. The example memory device includes an array...
US-9,940,989 STT-MRAM cell structures
A magnetic cell structure including a nonmagnetic bridge, and methods of fabricating the structure are provided. The magnetic cell structure includes a free...
US-9,940,988 Method of controlling a wordline
A method of controlling a wordline by a driver decoder circuit includes generating a first control signal having a first logically high level and a first...
US-9,940,987 High-speed word line decoder and level-shifter
A memory is provided that includes a row decoder that decodes an address into a plurality of decoded signals for selecting a word line to be asserted from a...
US-9,940,986 Electrostatic discharge protection structures for eFuses
The present disclosure relates to semiconductor structures and, more particularly, to electrostatic discharge (ESD) protection structures for eFuses. The...
US-9,940,985 Comparison operations in memory
The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of...
US-9,940,984 Shared command address (C/A) bus for multiple memory channels
A shared command/address (C/A) bus for memory devices in a multi-channel configuration can enable reducing the number of pins and signal lines in a memory...
US-9,940,983 Channel controlling device for improving data reading efficiency
A channel controlling device includes: a multiplexing circuit coupled to multiple channels for selecting a particular channel from the channels to output a...
US-9,940,982 Memory device having bank interleaving access
A memory device includes: a plurality of bank groups each comprising one or more banks; a first bus coupled to the plurality of bank groups; a second bus...
US-9,940,981 Division operations in memory
Examples of the present disclosure provide apparatuses and methods related to performing division operations in memory. An example apparatus might include a...
US-9,940,980 Hybrid LPDDR4-DRAM with cached NVM and flash-nand in multi-chip packages for mobile devices
An apparatus comprises a hybrid-memory multi-chip package (MCP) including a non-volatile memory (NVM) in an NVM die; a dynamic random access memory (DRAM) in...
US-9,940,979 Semiconductor device including a redistribution layer
A semiconductor device may include a first redistribution layer configured to allow for input and output of a first signal through the first redistribution...
US-9,940,978 Programmable memory device sense amplifier
Embodiments include circuits, apparatuses, and systems for programmable memory device sense amplifiers. In embodiments, an electronic circuit may include a...
US-9,940,976 Data storage library with component locker for environmental acclimation
A data storage library system and method comprising at least one data storage library, the at least one data storage library comprising one or more library...
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