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Patent # Description
US-9,953,985 Method of manufacturing integrated circuit device
A method of manufacturing an integrated circuit device includes forming multilayered stack structures that extend parallel to and separated from one another on...
US-9,953,984 Tungsten for wordline applications
Disclosed herein are methods and related apparatus for formation of tungsten wordlines in memory devices. Also disclosed herein are methods and related...
US-9,953,983 Vertical gate-all-around TFET
A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET...
US-9,953,982 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device includes the steps of: forming a shallow trench isolation (STI) in a substrate; removing part of the STI to form a...
US-9,953,981 Methods of manufacturing semiconductor devices having buried contacts and related semiconductor devices
A method of manufacturing a semiconductor device includes: forming bit line structures spaced apart from each other by first groove disposed in first direction,...
US-9,953,980 Operational amplifier circuit
In an output amplifier stage of an operational amplifier circuit, the first p-well of the first nMOSFET and the second p-well of the second nMOSFET are...
US-9,953,979 Contact wrap around structure
A semiconductor device includes a gate stack. The semiconductor device also includes a wrap-around contact arranged around and contacting substantially all...
US-9,953,978 Replacement gate structures for transistor devices
A transistor device includes a gate structure positioned above a semiconductor substrate, and spaced-apart sidewall spacers positioned above the substrate and...
US-9,953,977 FinFET semiconductor device
Fabricating a semiconductor structure, including: forming a fin structure on a substrate by: forming a first fin layer on the substrate; forming a first...
US-9,953,976 Effective device formation for advanced technology nodes with aggressive fin-pitch scaling
After forming a gate stack straddling a portion of each semiconductor fin of a plurality of semiconductor fins located over a substrate, a gate liner is formed...
US-9,953,975 Methods for forming STI regions in integrated circuits
A first Fin Field-Effect Transistor (FinFET) and a second FinFET are adjacent to each other. Each of the first FinFET and the second FinFET includes a...
US-9,953,974 Tipless transistors, short-tip transistors, and methods and circuits therefor
An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron and at least one...
US-9,953,973 Diode connected vertical transistor
An electrical device including a vertical transistor device connected to a vertical diode. The vertical diode connected transistor device including a vertically...
US-9,953,972 Semiconductor system, device and structure
An Integrated Circuit device, including: first transistors and second transistors, where the first transistors and the second transistors each include a single...
US-9,953,971 Insulated gate bipolar transistor (IGBT) and related methods
An insulated gate bipolar transistor (IGBT) includes a gate trench, an emitter trench, and an electrically insulative layer coupled to the emitter trench and...
US-9,953,970 Semiconductor device having ESD protection structure
The present disclosure relates to a semiconductor device with an ESD protection structure. The semiconductor device includes a high-voltage power device 101,...
US-9,953,969 Semiconductor power device having shielded gate structure and ESD clamp diode manufactured with less mask process
A semiconductor power device having shielded gate structure in an active area and having ESD clamp diode with two poly-silicon layer process is disclosed,...
US-9,953,968 Integrated circuit having an ESD protection structure and photon source
An integrated circuit having an ESD protection structure is described. One embodiment includes a circuit section interconnected with a first terminal and with a...
US-9,953,967 Integrated circuit with dual stress liner boundary
An integrated circuit with DSL borders perpendicular to the transistor gates primarily inside the nwell and with DSL borders parallel to the transistor gates...
US-9,953,966 Semiconductor device and method of forming the same
A semiconductor device having a semiconductor substrate is provided. The semiconductor substrate includes an integrated circuit, which includes multi-layer...
US-9,953,965 Semiconductor package
A semiconductor package may include a DRAM chip mounted on a substrate; an interposer stacked over the DRAM chip and including redistribution structures; a...
US-9,953,964 Method for manufacturing semiconductor package
A method for manufacturing a semiconductor package including providing a first semiconductor package including a first package substrate and a first solder...
US-9,953,963 Integrated circuit process having alignment marks for underfill
Packages having alignment marks and methods of forming the same are provided. A first workpiece is attached to a second workpiece. The first workpiece has an...
US-9,953,961 Semiconductor device and method for manufacturing the same
A semiconductor device can reduce the number of bonding wires. The semiconductor device includes two or more semiconductor elements each of which has electrodes...
US-9,953,960 Manufacturing process of wafer level chip package structure having block structure
A multi-chip package structure includes a first chip, at least one blocking structure, a plurality of first conductive bumps, a second chip, a plurality of...
US-9,953,959 Metal protected fan-out cavity
A metal protected fan-out cavity enables assembly of a package-on-package (PoP) integrated circuit while reducing PoP solder spacing and overall z-height. A...
US-9,953,958 Electronic component device
An electronic component device includes a first electronic component, a second electronic component disposed on and connected to the first electronic component,...
US-9,953,957 Embedded graphite heat spreader for 3DIC
A device with thermal control is presented. In some embodiments, the device includes a plurality of die positioned in a stack, each die including a chip,...
US-9,953,956 Package substrate and package structure using the same
A package substrate is provided. The package substrate includes a base layer having a first surface and a second surface opposite to the first surface, a...
US-9,953,955 Integrated fan-out package structures with recesses in molding compound
A package includes a first die and a second die. The first die includes a first substrate and a first metal pad overlying the first substrate. The second die...
US-9,953,954 Wafer-level chip-scale package with redistribution layer
A Wafer-level chip scale package (WLCSP) includes a semiconductor structure and a first bonding pad formed over a portion of the semiconductor structure. The...
US-9,953,953 Method for assembling a microelectronic chip element on a wire element, and installation enabling assembly to...
Method for assembling includes: providing a system to transfer wire element from wire element supply device to wire element storage device; stretching wire...
US-9,953,952 Semiconductor device having a sealant layer including carbon directly contact the chip and the carrier
A semiconductor device includes a carrier, a chip attached to the carrier, a sealant vapor deposited over the chip and the carrier, and encapsulation material...
US-9,953,951 Method of providing a flexible semiconductor device and flexible semiconductor device thereof
Some embodiments include a method. The method can comprise: providing a carrier substrate; providing an adhesion modification layer over the carrier substrate;...
US-9,953,950 Nitride-enriched oxide-to-oxide 3D wafer bonding
A semiconductor structure comprising a first semiconductor structure; a second semiconductor structure; and a silicon-nitride layer configured to bond the first...
US-9,953,949 Through package via (TPV)
A through package vias (TPV), a package including a plurality of the TPVs, and a method of forming the through package via are provided. Embodiments of a...
US-9,953,948 Pillar design for conductive bump
A system and method for conductive pillars is provided. An embodiment comprises a conductive pillar having trenches located around its outer edge. The trenches...
US-9,953,946 Die-bonding layer formation film, processed product having die-bonding layer formation film attached thereto,...
A die-bonding layer formation film to be used for fixing a processed product to an adherend, includes an adhesive layer, wherein, the storage elastic modulus...
US-9,953,945 Adhesive resin compostition for bonding semiconductors and adhesive film for semiconductors
The present invention relates to an adhesive resin composition for bonding semiconductors, including: a (meth)acrylate-based resin including more than 17% by...
US-9,953,944 Power module
A power module is disclosed, including a power module substrate in which a circuit layer is arranged on one surface of an insulating layer; and a semiconductor...
US-9,953,943 Semiconductor apparatus having multiple ranks with noise elimination
A semiconductor apparatus includes a plurality of dies. Any one of the dies may be set to a first rank and another of the dies may be set to a second rank. One...
US-9,953,942 Semiconductor packaging and manufacturing method thereof
The present disclosure provides a semiconductor package, which includes a substrate, a passivation layer, a post-passivation interconnect (PPI) having a top...
US-9,953,941 Conductive barrier direct hybrid bonding
A method for forming a direct hybrid bond and a device resulting from a direct hybrid bond including a first substrate having a first set of metallic bonding...
US-9,953,940 Corrosion resistant aluminum bond pad structure
A method of manufacturing a bond pad structure may include depositing an aluminum-copper (Al--Cu) layer over a dielectric layer; and depositing an ...
US-9,953,939 Conductive contacts having varying widths and method of manufacturing same
A bump structure includes a contact element formed on a substrate and a passivation layer overlying the substrate. The passivation layer includes a passivation...
US-9,953,938 Tunable active silicon for coupler linearity improvement and reconfiguration
An electromagnetic coupler assembly includes a handle wafer having an oxide layer disposed on a first surface thereof. A layer of active semiconductor is...
US-9,953,937 Electronic device and method of producing the same
An electronic device includes a structure including a first resin layer, an electronic component buried in the first resin layer, a reflector element for...
US-9,953,936 Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a transceiver configured to communicate with a device, a molding surrounding the transceiver, a via extending through the...
US-9,953,935 Packaging for high speed chip to chip communication
Disclosed are chip packaging structures for high speed chip to chip and chip to carrier communications and methods of making such structures. The chip packaging...
US-9,953,934 Warpage controlled package and method for same
A warp controlled package includes a substrate that assumes a warped configuration according to the application of heat. At least one device is coupled along...
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