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Patent # Description
US-9,953,933 Flow over wire die attach film and conductive molding compound to provide an electromagnetic interference...
A semiconductor package includes a substrate, a die, an insulating die attach film, a dummy die, a conductive layer, and an electrically conductive molding...
US-9,953,932 Electronic circuit package
Disclosed herein is an electronic circuit package includes: a substrate having a power supply pattern; an electronic component mounted on a surface of the...
US-9,953,931 Semiconductor device package and a method of manufacturing the same
A semiconductor device package comprises a substrate, a first electronic component, first and second conductive pads, a first frame board, an encapsulation...
US-9,953,930 Semiconductor package structure and method for manufacturing the same
A semiconductor package structure includes a substrate, a semiconductor element, an encapsulant, an adhesion layer and a metal cap. The semiconductor element is...
US-9,953,929 Systems and methods for electromagnetic interference shielding
Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include a substrate...
US-9,953,928 Semiconductor devices including empty spaces
Semiconductor devices including empty spaces and methods of forming the semiconductor devices are provided. The semiconductor devices may include first and...
US-9,953,927 Liner replacements for interconnect openings
Structures for a liner replacement in an interconnect structure and methods for forming a liner replacement in an interconnect structure. A metallization level...
US-9,953,926 Methods of depositing cobalt manganese films
Described are semiconductor devices and methods of making semiconductor devices with a barrier layer comprising cobalt and manganese nitride. Also described are...
US-9,953,925 Semiconductor system and device
A 3D IC device including: a first semiconductor layer including first mono-crystallized transistors, where the first mono-crystallized transistors are...
US-9,953,924 Semiconductor devices including a capping layer
Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on...
US-9,953,923 Metallization stack and semiconductor device and electronic device including the same
A metallization stack, comprising: at least an interlayer dielectric layer comprising a dielectric material and a negative capacitance material, wherein: at...
US-9,953,922 Semiconductor device, method for manufacturing the same, method for generating mask data, mask and computer...
A multilayer semiconductor device includes first wirings extending in a first direction adjacent to each other in a second direction. Dummy wirings are arranged...
US-9,953,921 Semiconductor device and semiconductor package
A semiconductor device may include a first metal line; a second metal line; a first insulating layer formed between the first metal line and the second metal...
US-9,953,920 Interconnect structure and method
An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first photo-sensitive dielectric layer formed over the interlayer...
US-9,953,919 Semiconductor device including fuse structure
An eFuse structure of a semiconductor device may include a first metal formed at a first level on a substrate, a second metal formed at a second level between...
US-9,953,918 Method of fabricating anti-fuse for silicon on insulator devices
A method includes depositing a first hard mask layer on a first substrate; lithographically patterning and etching the first substrate to form a semiconductor...
US-9,953,917 Electronics package with embedded through-connect and resistor structure and method of manufacturing thereof
An electronics package includes an insulating substrate, a semiconductor device having a top surface coupled to a first side of the insulating substrate, and a...
US-9,953,916 Critical dimension shrink through selective metal growth on metal hardmask sidewalls
A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask...
US-9,953,915 Electrically conductive interconnect including via having increased contact surface area
An interconnect structure includes a first dielectric layer and a second dielectric layer each extending along a first axis to define a height and a second axis...
US-9,953,914 Substrate-less stackable package with wire-bond interconnect
A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a...
US-9,953,913 Electronics package with embedded through-connect structure and method of manufacturing thereof
An electronics package includes an insulating substrate, a semiconductor device having a top surface coupled to a first side of the insulating substrate, and a...
US-9,953,912 Work pieces and methods of laser drilling through holes in substrates using an exit sacrificial cover layer
Work pieces and methods of forming through holes in substrates are disclosed. In one embodiment, a method of forming a through hole in a substrate by drilling...
US-9,953,911 Fan-out package structure and method
A method includes attaching a semiconductor structure on a carrier, depositing a molding compound layer over the carrier, wherein the semiconductor structure is...
US-9,953,910 Demountable interconnect structure
An electronic component includes a base insulative layer having first and second surfaces; an electronic device having first and second surfaces; at least one...
US-9,953,909 Ball grid array (BGA) with anchoring pins
Embodiments herein may relate to an electronic device that includes a board. The electronic device may include a device physically coupled with the board by an...
US-9,953,908 Method for forming solder bumps using sacrificial layer
A barrier layer is formed over electrically conductive contact pads on a substrate such as a wafer. A photoresist layer is applied over the barrier layer, and...
US-9,953,907 PoP device
A method of forming a PoP device comprises placing an adhesive layer on a carrier substrate, coupling a plurality of chip packages to the adhesive layer on the...
US-9,953,906 Method of manufacturing element chip, method of manufacturing electronic component-mounted structure, and...
In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate...
US-9,953,905 Semiconductor device
A semiconductor device includes a substrate, a semiconductor element, a terminal and a solder outflow prevention part. The semiconductor element is fixed on one...
US-9,953,904 Electronic component package with heatsink and multiple electronic components
An electronic component package that includes a heat spreader with a die pad. An electronic component is attached to each side of the die pad where each...
US-9,953,903 Heatsink very-thin quad flat no-leads (HVQFN) package
Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device having enhanced heat dissipation. The method comprises...
US-9,953,902 Semiconductor device including semiconductor chips electrically connected via a metal plate
A semiconductor device includes first and second conductive layers on a substrate and separated from each other. A first semiconductor chip is mounted on the...
US-9,953,901 Semiconductor light emitting device and method for manufacturing the same
A semiconductor light emitting device includes a semiconductor light source, a resin package surrounding the semiconductor light source, and a lead fixed to the...
US-9,953,900 Transistor structures gated using a conductor-filled via or trench
Device structures involving a conductor-filled via or trench, methods of forming such device structures, and methods of operating such device structures. A...
US-9,953,899 Micro heat transfer arrays, micro cold plates, and thermal management systems for cooling semiconductor...
Embodiments of the present invention are directed to heat transfer arrays, cold plates including heat transfer arrays along with inlets and outlets, and thermal...
US-9,953,898 Flow channel member, and heat exchanger and semiconductor module each using same
A flow channel member according to the present invention includes a ceramic substrate, a flow channel inside the ceramic substrate through which a fluid flows,...
US-9,953,897 Fluid-filled microchannels
A device comprises a first layer of a die. The first layer comprises a microchannel. The microchannel is partially filled with a liquid and partially filled...
US-9,953,896 Heat dissipating module, heat dissipating system and circuit module
The present application provides a heat dissipating module, a heat dissipating system and a circuit module. The heat dissipating module adapted to be used with...
US-9,953,895 Heat pipe and method of manufacturing the same
A method of manufacturing a heat pipe, including the steps of: forming in a substrate a cylindrical opening provided with a plurality of ring-shaped recessed...
US-9,953,894 Semiconductor device and manufacturing method thereof
A semiconductor device including: a semiconductor element, a substrate having a first surface on which the semiconductor element is provided, and a second...
US-9,953,893 Power electronic assembly
A method of producing a power electronic assembly and a power electronic assembly including a power electronic module incorporating multiple of semiconductor...
US-9,953,892 Polymer based-semiconductor structure with cavity
A structure includes a device die, and an encapsulating material encapsulating the device die therein. The encapsulating material has a top surface coplanar...
US-9,953,891 Method of forming post-passivation interconnect structure
A method includes coating a passivation layer overlying a semiconductor substrate and forming an interconnect layer overlying the passivation layer. The...
US-9,953,890 Semiconductor device
A semiconductor device includes an insulating substrate on which semiconductor elements are mounted and a surrounding case in which the insulating substrate is...
US-9,953,889 Process for making semiconductor dies, chips, and wafers using non-contact measurements obtained from DOEs of...
Improved processes for manufacturing semiconductor wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements ("NCEM") of...
US-9,953,888 Electromagnetic detection device and semiconductor manufacturing system
An electromagnetic detection device is provided. The electromagnetic detection device includes an induction coil, a converter, and a controller. The induction...
US-9,953,887 Measuring individual layer thickness during multi-layer deposition semiconductor processing
In situ wafer metrology is conducted to reliably obtain deposition thickness for each successive layer in a multi-layer deposition. A wafer to be processed is...
US-9,953,886 Single-wafer real-time etch rate and uniformity predictor for plasma etch processes
The present disclosure relates to semiconductor manufacturing, in particular to a real-time method for qualifying the etch rate for plasma etch processes. A...
US-9,953,885 STI shape near fin bottom of Si fin in bulk FinFET
A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming a first insulation region and...
US-9,953,884 Field effect transistor including strained germanium fins
In one example, a device includes a p-type field effect transistor region and n-type field effect transistor region. The p-type field effect transistor region...
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