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Patent # Description
US-9,953,729 Radiation generating apparatus and radiation generating method
A radiation generating apparatus comprises a fuel storage unit 20 for storing a mixed liquid 61, a pressure application unit 10 for applying a pressure to the...
US-9,953,728 Redundant column or row in resistive random access memory
Examples include a resistive random access memory (RRAM) array to support a redundant column. Some examples include an RRAM cell at a cross point of a column...
US-9,953,727 Circuit and method for detecting time dependent dielectric breakdown (TDDB) shorts and signal-margin testing
The present disclosure relates to a structure which includes a twin-cell memory which is configured to program a plurality of write operations, a current sense...
US-9,953,726 Fast quasi-parity checker for correlated electron switch (CES) memory array
An apparatus is provided for testing storage elements that include a variable impedance element switchable between a first impedance state and a second...
US-9,953,725 Semiconductor memory devices and methods of operating the same
A method of operating a semiconductor memory device is provided. In a method of operating a semiconductor memory device including a memory cell array which...
US-9,953,724 Memory devices and methods for managing error regions
Memory devices and methods are described that include a stack of memory dies and a logic die. Method and devices described include those that provide for...
US-9,953,723 Input/output terminal characteristic calibration circuit and semiconductor apparatus including the same
An input/output terminal characteristic calibration circuit may include a plurality of input/output terminals a subset of which is configured to partially and...
US-9,953,722 Methods of system optimization by over-sampling read
A method of controller optimization utilizing over-sampling read (OSR) in a memory device includes performing a first internal read at a predetermined threshold...
US-9,953,721 Gate driver circuit, touch display device and touch display driving method
Embodiments of the present invention provide a gate driver circuit, a touch display device and a touch display driving method. The gate driver circuit includes...
US-9,953,720 Implementing hidden security key in eFuses
A method and circuit for implementing a hidden security key in Electronic Fuses (eFuses), and a design structure on which the subject circuit resides are...
US-9,953,719 Flash memory cell and associated decoders
The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The...
US-9,953,718 Programming memory cells to be programmed to different levels to an intermediate level from a lowest level
First memory cells are programmed to an intermediate level from a lowest level, corresponding to a lowest data state, where the first memory cells are to be...
US-9,953,717 NAND structure with tier select gate transistors
Systems and methods for improving performance of a non-volatile memory by utilizing one or more tier select gate transistors between different portions of a...
US-9,953,716 Non-volatile semiconductor storage device
According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining...
US-9,953,715 Level shifter
According to one embodiment, A level shifter includes a first circuit configured to generate a first signal, the first signal being inverted and delayed signal...
US-9,953,714 Semiconductor device
A semiconductor device includes a first circuit configured to generate a first voltage based on a first current, a second circuit that includes a first...
US-9,953,713 Nonvolatile semiconductor memory device
When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second...
US-9,953,712 Nonvolatile memory device and storage device including the nonvolatile memory device
A nonvolatile memory device includes a memory cell array having memory cells, a row decoder circuit connected to the memory cells through word lines, a page...
US-9,953,711 Methods of operating memory under erase conditions
Methods of operating a memory include applying a first voltage level to a first semiconductor material of a first conductivity type forming a channel region for...
US-9,953,710 Memory devices with a connecting region having a band gap lower than a band gap of a body region
Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region....
US-9,953,709 Semiconductor memory device and memory system
According to one embodiment, a semiconductor memory device includes a cell transistor coupled to a word line, a sense amplifier configured to output data based...
US-9,953,708 Memory performing write operation in which a string transistor channel voltage is boosted before applying a...
A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first...
US-9,953,707 Memory device
According to one embodiment, a memory device includes a sense amplifier including a first input node and a second input node, a first path including a memory...
US-9,953,706 Method and apparatus for faster determination of cell state of a resistive memory cell using a parallel resistor
A device for determining an actual cell state of a resistive memory cell having a plurality M of programmable cell states comprising a sensing circuit, a...
US-9,953,705 Planar memory cell architectures in resistive memory devices
To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a...
US-9,953,704 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit...
US-9,953,703 Programming method of non volatile memory device
Provided is a programming method of a nonvolatile memory device including a plurality of memory cells. The programming method of the nonvolatile memory device...
US-9,953,702 Semiconductor memory devices, memory systems including the same and methods of operating the same
A semiconductor memory device includes a memory cell array, a control logic circuit, an internal processing circuit, and an error correction circuit. The...
US-9,953,701 SRAM architecture with bitcells of varying speed and density
An SRAM with a first bitcell array having a first density and a first access speed, and a second bitcell array having a second density larger than the first...
US-9,953,700 Data output circuit and semiconductor memory device including the same
A data output circuit includes: a first data latch unit enabled in response to a first bank selection signal including clock information, for storing first...
US-9,953,699 Static random access memory (SRAM) assist circuit
The present disclosure relates to semiconductor structures and, more particularly, to a static random access memory assist circuit and methods of implementation...
US-9,953,698 Overvoltage protection for a fine grained negative wordline scheme
A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including...
US-9,953,697 Volatile memory device employing a resistive memory element
A volatile resistive memory device includes a resistive memory element including a barrier material portion and a charge-modulated resistive memory material...
US-9,953,696 Refresh control circuit for target refresh operation of semiconductor memory device, and operating method thereof
A semiconductor memory device may include: a memory cell region including a plurality of memory cells coupled between a plurality of word lines and a plurality...
US-9,953,695 Semiconductor device, electronic device, and semiconductor wafer
A semiconductor device capable of stably holding data for a long time is provided. A transistor including a back gate is used as a writing transistor of a...
US-9,953,694 Memory controller-controlled refresh abort
A memory subsystem enables a refresh abort command. A memory controller can issue an abort for an in-process refresh command sent to a memory device. The...
US-9,953,693 Fast exit from DRAM self-refresh
Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low...
US-9,953,692 Spin orbit torque MRAM memory cell with enhanced thermal stability
An in-plane SOT MRAM non-volatile memory cell has enhanced thermal stability due to coercive pinning provided by an adjacent antiferromagnetic layer that has a...
US-9,953,690 Apparatuses, methods, and systems for stochastic memory circuits using magnetic tunnel junctions
Embodiments include apparatuses, systems, and methods including a memory apparatus including a plurality of bit cells, wherein each of the plurality of bit...
US-9,953,689 Memory device, related method, and related electronic device
A memory device may include the following elements: a first memory cell; a first word line for transmitting a first control signal to control an electrical...
US-9,953,688 Precharge control device and semiconductor device including the same
A precharge control device includes a pulse generator, a bank address controller, and a precharge signal generator. The pulse generator generates a write...
US-9,953,687 Pseudo-dynamic circuit for multi-voltage timing interlocks
An interlock circuit utilizes a single combinatorial pseudo-dynamic logic gate to take inputs from two voltage domains at the same time without requiring either...
US-9,953,686 Memory system and data transmission method
A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in...
US-9,953,685 Semiconductor device and method for fabricating the same
A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a substrate, a memory device, and a select...
US-9,953,684 Adhesive cover seal for hermetically-sealed data storage device
A method of assembling a data storage device comprises forming an enclosure by overlapping each of a plurality of sidewalls of a cover with a corresponding...
US-9,953,683 Die-cut gasket manufacturing
A method for manufacturing gaskets is described herein that includes cutting at least one hole in a first material, wherein the at least one hole corresponds to...
US-9,953,682 Apparatus and method for providing sensory effects for vestibular rehabilitation therapy
A system for providing sensory effects according to an embodiment of the present invention comprises an apparatus for providing vestibular rehabilitation videos...
US-9,953,681 System and method for representing long video sequences
Systems and procedures for transforming video into a condensed visual representation. An example procedure may include receiving video comprised of a plurality...
US-9,953,680 Mobile terminal and method for controlling the same
The present invention relates to a mobile terminal capable of capturing videos, and a method of controlling the same. The mobile terminal includes a display...
US-9,953,679 Systems and methods for generating a time lapse video
Images may be extracted from a video. The images may be grouped into image groups. Numbers and types of classified visuals within the images may be detected....
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