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Patent # Description
US-9,960,185 Base and manufacturing method thereof, display device
A base and a manufacturing method thereof and a display device are provided, so that a problem of faultage of an insulating layer when forming the insulating...
US-9,960,184 FDSOI-capacitor
A semiconductor device includes a semiconductor-on-insulator (SOI) wafer having a semiconductor substrate, a buried insulating layer positioned above the...
US-9,960,183 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device including: preparing a substrate in which an insulating layer, a semiconductor layer, and an insulating film...
US-9,960,182 Three-dimensional semiconductor memory device and method of fabricating the same
A semiconductor memory device includes a stack including gate electrodes sequentially stacked on a substrate, a vertical insulating structure penetrating the...
US-9,960,181 Three-dimensional memory device having contact via structures in overlapped terrace region and method of making...
Contact areas for three-dimensional memory devices including multiple vertically stacked tier structures can be reduced by overlapping stepped terraces of the...
US-9,960,180 Three-dimensional memory device with partially discrete charge storage regions and method of making thereof
Memory openings can be formed through an alternating stack of insulating layers and sacrificial material layers. Memory stack structures including charge...
US-9,960,179 Semiconductor memory device and method for manufacturing same
A semiconductor memory device includes a conductive layer; electrode layers stacked on the conductive layer; an insulating body extending through the electrode...
US-9,960,178 Semiconductor memory device and method for manufacturing same
According to one embodiment, a semiconductor memory device includes a stacked body and a column. The stacked body includes a plurality of electrode layers. The...
US-9,960,177 Semiconductor device and manufacturing method of the same
A semiconductor device includes a substrate including a cell region and a peripheral region, a cell stacked structure stacked on the substrate in the cell...
US-9,960,176 Nitride-free spacer or oxide spacer for embedded flash memory
In some embodiments, a semiconductor substrate includes first and second source/drain regions which are separated from one another by a channel region. The...
US-9,960,175 Field effect transistor memory device
A method for generating a non-volatile memory device may comprise: applying plasma for a preset time period to an exposed surface of a channel of a field effect...
US-9,960,174 Semiconductor device and method for manufacturing the same
According to one embodiment, a semiconductor device includes a semiconductor layer; an electrode layer; a first insulating film; a charge storage film; and a...
US-9,960,173 Semiconductor memory device
According to one embodiment, a semiconductor memory device includes: a substrate; a first interconnect; a second interconnect; a plurality of third...
US-9,960,172 Reliable non-volatile memory device
Device and method for forming a device are disclosed. The method includes providing a substrate prepared with a memory cell region. At least first and second...
US-9,960,171 Semiconductor devices including charge storage patterns
Semiconductor devices are provided. A semiconductor device includes a plurality of gate electrodes. The semiconductor device includes a channel structure...
US-9,960,170 Methods of fabricating memory devices
Methods of fabricating a memory device are provided. The methods may include forming a mask pattern including line-shaped portions that are parallel to each...
US-9,960,169 Methods of manufacturing semiconductor devices
In a method of manufacturing a semiconductor device, mask patterns are formed on a semiconductor substrate. An organic layer is formed on the semiconductor...
US-9,960,168 Capacitor strap connection structure and fabrication method
Structures and methods for deep trench capacitor connections are disclosed. The structure includes a reduced diameter top portion of the capacitor conductor....
US-9,960,167 Method for forming semiconductor device
A method for forming a semiconductor device includes providing a substrate having a plurality of memory cells formed therein; forming an insulating layer on the...
US-9,960,166 Method of operating semiconductor memory device with floating body transisor using silicon controlled rectifier...
Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are...
US-9,960,165 Semiconductor device having adjacent IGBT and diode regions with a shifted boundary plane between a collector...
Provided is a technology for further reducing a loss in a semiconductor device including a semiconductor substrate in which an IGBT region and a diode region...
US-9,960,164 Flipped vertical field-effect-transistor
Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an...
US-9,960,163 Method for fabricating fin-shaped structure and bump made of different material
A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first fin-shaped structure and a bump are formed on the substrate,...
US-9,960,162 Hybrid high-k first and high-k last replacement gate process
An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric...
US-9,960,161 Low resistive electrode for an extendable high-k metal gate stack
In one embodiment, a method of making a semiconductor device includes: forming a substrate; forming an nFET transistor and a pFET transistor on the substrate;...
US-9,960,160 Method of forming a single metal that performs N work function and P work function in a high-k/metal gate process
The present disclosure describes a semiconductor device. The device includes a semiconductor substrate, an isolation structure formed in the substrate for...
US-9,960,159 Monolithic bi-directional current conducting device and method of making the same
A monolithic bi-directional device provides bi-directional power flow and bi-directional blocking of high-voltages. The device includes a first transistor...
US-9,960,158 Semiconductor device
A semiconductor device includes a multilayer structure including an n- i layer, a p anode layer formed on the front surface of the n- i layer, an n- buffer...
US-9,960,157 Bidirectional normally-off III-V high electron mobility transistor (HEMT)devices and circuits
Circuits and devices for bidirectional normally-off switches are described. A circuit for a bidirectional normally-off switch includes a depletion mode...
US-9,960,156 Integrated semiconductor device having a level shifter
An integrated semiconductor device is provided. According to an embodiment, the integrated semiconductor device includes a semiconductor body having a first...
US-9,960,155 Laterally diffused metal oxide semiconductor device integrated with vertical field effect transistor
An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal...
US-9,960,154 GaN structures
A semiconductor device is disclosed. The device includes a substrate including GaN, a two dimensional electron gas (2DEG) inducing layer on the substrate, and a...
US-9,960,153 Semiconductor device and electronic apparatus of a cascode-coupled system
The manufacturing yield of a semiconductor device is improved. There is provided a semiconductor device of a cascode coupling system, which is equipped with a...
US-9,960,152 Optoelectronic device with light-emitting diodes comprising at least one zener diode
An optoelectronic device is provided, including light-emitting diodes arranged such that: N diodes of said plurality, where N .gtoreq.2, are connected in series...
US-9,960,151 Semiconductor device, display panel assembly, semiconductor structure
A semiconductor device includes a chip, a plurality of first bumps, and a plurality of second bumps. The chip includes an active surface. The first bumps are...
US-9,960,150 Semiconductor device assembly with through-mold cooling channel formed in encapsulant
Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one...
US-9,960,149 Devices and stacked microelectronic packages with package surface conductors and methods of their fabrication
Embodiments of methods for forming a device include performing an oxidation inhibiting treatment to exposed ends of first and second device-to-edge conductors,...
US-9,960,148 Methods for transferring heat from stacked microfeature devices
Methods and apparatuses for transferring heat from stacked microfeature devices are disclosed herein. In one embodiment, a microfeature device assembly...
US-9,960,147 Power module
A power module includes a base plate, first, second, and third semiconductor chips. At least one of a third edge or fourth edge of the first semiconductor chip...
US-9,960,146 Semiconductor structure and method for forming the same
A semiconductor structure includes a first stacking interposer. The first stacking interposer includes a first interposer having a first surface and a second...
US-9,960,145 Flip chip module with enhanced properties
A flip chip module having at least one flip chip die is disclosed. The flip chip module includes a carrier having a top surface with a first mold compound...
US-9,960,144 Method for heating a metal member, method for bonding heated metal members, and apparatus for heating a metal...
A heating method includes an oxide film forming step and a heating step. The thickness of an oxide film is set in a first range that includes a first maximal...
US-9,960,143 Method for manufacturing electronic component and manufacturing apparatus of electronic component
A method for manufacturing an electronic component includes positioning a first surface of a first component facing a second surface of a second component in a...
US-9,960,142 Hybrid bonding with air-gap structure
A package component includes a surface dielectric layer having a first planar surface, and a metal pad in the surface dielectric layer. The metal pad includes a...
US-9,960,141 Binding wire and semiconductor package structure using the same
A semiconductor package structure includes a substrate, and a package preform. The substrate includes a plurality of conductive tracing wires. The package...
US-9,960,140 Metal joining structure using metal nanoparticles and metal joining method and metal joining material
The present invention can give a joining structure using metal nanoparticles to join the same types or different types of metal where when one surface metal is...
US-9,960,139 Anisotropic conductive film, method for producing anisotropic conductive film, method for producing connection...
To reduce substrate warp occurring after connection an anisotropic conductive film is used. An anisotropic conductive film has: a first insulating adhesive...
US-9,960,138 Connection body
Even in case of conductive particles being clamped between stepped sections of substrate electrodes and electrode terminals, conductive particles sandwiched...
US-9,960,137 Semiconductor device package and method for forming the same
A semiconductor device package ready for assembly includes: a semiconductor substrate; a first under-bump-metallurgy (UBM) layer disposed on the semiconductor...
US-9,960,136 Semiconductor device and method for manufacturing the same
A semiconductor device includes a first circuit layer, a copper pillar disposed adjacent to the first circuit layer, a second circuit layer and a solder layer....
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