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Patent # Description
US-9,960,135 Metal bond pad with cobalt interconnect layer and solder thereon
A method of forming bond pads includes providing a substrate including an integrated circuit (IC) device formed thereon having an oxidizable uppermost metal...
US-9,960,134 Semiconductor device and bump formation process
A semiconductor device includes a solder bump overlying and electrically connected to a pad region, and a metal cap layer formed on at least a portion of the...
US-9,960,133 Filter and capacitor using redistribution layer and micro bump layer
An integrated circuit package includes a die. An electrically conductive layer comprises a redistribution layer (RDL) in the die, or a micro-bump layer above...
US-9,960,132 Display apparatus and method for binding the same
Embodiments of the present application provide a display apparatus and a method for binding the same. The apparatus includes: a flexible display panel; and a...
US-9,960,131 Method for thermo-mechanical stress reduction in semiconductor devices and corresponding device
In one embodiment, a semiconductor device includes one or more metallizations, such as, e.g., Cu-RDL metallizations, provided on a passivation layer over a...
US-9,960,130 Reliable interconnect
Devices and methods for forming a device are disclosed. The device includes a contact region disposed over a last interconnect level of the device. The device...
US-9,960,129 Hybrid bonding mechanisms for semiconductor wafers
A method of forming a hybrid bonding structure includes depositing an etch stop layer over surface of a substrate, wherein the substrate comprises a conductive...
US-9,960,128 Fan-out semiconductor package
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an...
US-9,960,127 High-power amplifier package
Package assemblies for improving heat dissipation of high-power components in microwave circuits are described. A laminate that includes microwave circuitry may...
US-9,960,126 Semiconductor device
According to the present invention, a semiconductor device includes a heat spreader, a semiconductor chip fixed to a mounting surface of the heat spreader via a...
US-9,960,124 Integrated shield structure for mixed-signal integrated circuits
In certain embodiments, a mixed signal integrated circuit is provided that includes both a digital portion and an analog portion. A shield is provided that...
US-9,960,123 Method of forming semiconductor structure with aligning mark in dicing region
The present invention provides a method of forming a semiconductor structure. A wafer with a dicing region is provided, the dicing region comprises a central...
US-9,960,122 Composite device with substrate and mounted component
A composite device includes a substrate and a mounted component mounted on a surface of, or inside, the substrate. The substrate includes a first thermoplastic...
US-9,960,121 Semiconductor device having conductive via and manufacturing process for same
In accordance with the present invention, there is provided a semiconductor device comprising a semiconductor die or chip, a package body and a through package...
US-9,960,120 Wiring substrate with buried substrate having linear conductors
A wiring substrate includes a buried substrate disposed within a through-hole penetrating through a resin substrate of a core layer and including a plate-like...
US-9,960,119 Method and structure for wafer level packaging with large contact area
A method to provide a wafer level package with increasing contact pad area comprising the steps of forming a first packaging layer on wafer top surface,...
US-9,960,118 Contact using multilayer liner
An opening is formed within a substrate made of a silicon material, and a cleaning process is performed; after which, the bottom and walls of the opening are...
US-9,960,117 Air gap semiconductor structure with selective cap bilayer
A semiconductor substrate including one or more conductors is provided. A first layer and a second layer are deposited on the top surface of the conductors. A...
US-9,960,116 Semiconductor device and manufacturing method thereof
A resistor whose characteristic value can be changed without requiring a photolithography process again is provided. The resistor includes a plurality of first...
US-9,960,115 Heat dissipation and series resistance reduction of PA and RF switch in SLT by backside thick metal
Methods of forming a SOI PA and RF switch device having a thin BOX layer in the PA power cell region and a thick metal layer directly under the thin BOX layer...
US-9,960,114 Structure of integrated circuitry and a method of forming a conductive via
A method of forming a conductive via comprises forming a structure comprising an elevationally-extending-conductive via and a conductive line electrically...
US-9,960,113 Method to fabricate a high performance capacitor in a back end of line (BEOL)
A method can include applying a patterned mask over a semiconductor structure, the semiconductor structure having a dielectric layer, forming using the...
US-9,960,112 Semiconductor device
A semiconductor device comprising: a substrate; a decoupling capacitor disposed on the substrate; a first connection pad vertically overlapping with the...
US-9,960,111 Mechanisms for forming metal-insulator-metal (MIM) capacitor structure
A method for forming a metal-insulator-metal (MIM) capacitor structure is provided. The method includes providing a substrate and forming an interconnect...
US-9,960,110 Self-enclosed asymmetric interconnect structures
Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. The...
US-9,960,109 Printed circuit board and electronic equipment
A plurality of lands is formed apart from each other on a surface of a package substrate. Another plurality of lands is formed apart from each other on a...
US-9,960,107 Package substrate, method for fabricating the same, and package device including the package substrate
A package substrate including an insulating layer having a top surface and a bottom surface opposite to the top surface, at least one first copper pattern...
US-9,960,106 Package with metal-insulator-metal capacitor and method of manufacturing the same
A package includes a chip formed in a first area of the package and a molding compound formed in a second area of the package adjacent to the first area. A...
US-9,960,105 Controlled solder height packages and assembly processes
An apparatus comprises a substrate including a surface and a plurality of bonding pads positioned on the surface. The apparatus also includes a material...
US-9,960,104 Integrated package design with wire leads for package-on-package product
An integrated package design for a package-on-package product is described that uses wire leads. Some embodiments pertain to a stacked package assembly that...
US-9,960,103 Power module semiconductor device and inverter equipment, and fabrication method of the power module...
The power module semiconductor device (2) includes: an insulating substrate (10); a first pattern (10a) (D) disposed on the insulating substrate (10); a...
US-9,960,102 Semiconductor devices and methods of manufacturing the same
A semiconductor package includes a first semiconductor component, a second semiconductor component, and a connecting element. The first semiconductor component...
US-9,960,101 Micro-hoses for integrated circuit and device level cooling
A heat-dissipating device includes at least one heat-dissipating surface and a micro-sized cooling mechanism formed directly on the heat-dissipating surface by...
US-9,960,100 Cooler and semiconductor module using same
A cooler includes: a jacket having an internal coolant conduction space surrounded by a main cooling surface top plate, an opposite bottom plate, and a side...
US-9,960,099 Thermally conductive molding compound structure for heat dissipation in semiconductor packages
A method of forming a semiconductor package includes forming a thermal conductivity layer and attaching the thermal conductivity layer to a chip. The chip has a...
US-9,960,098 Systems and methods for thermal conduction using S-contacts
An integrated circuit architecture that provides a path having relatively low thermal resistance between one or more electronic devices and one or more thermal...
US-9,960,097 Semiconductor device
A semiconductor device manufacturing method includes a step of preparing a semiconductor unit, having a first main surface including a heat releasing portion...
US-9,960,096 Semiconductor device
In a semiconductor device, a second heat sink and a third heat sink are electrically connected by a joint portion in an alignment direction in which a first...
US-9,960,095 Thermally enhanced semiconductor package with thermal additive and process for making the same
The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a...
US-9,960,094 Packaged semiconductor components having substantially rigid support members and methods of packaging...
Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member...
US-9,960,093 Packaging structure, packaging method and template used in packaging method
Disclosed are a packaging structure, a packaging method and a template used in packaging method. The packaging structure comprises: a substrate; a chip mounted...
US-9,960,092 Interlayer filler composition for three-dimensional integrated circuit
To provide an interlayer filler composition which, in 3D lamination of semiconductor device chips, forms a highly thermally conductive filling interlayer...
US-9,960,091 Package
A package includes: a semiconductor element; a case having an opening and housing the semiconductor element; and a lid having a rectangular parallelepiped shape...
US-9,960,090 Display panel and method of manufacturing the same
A display panel includes first and second test lines connected to the each of data lines, extending in the second direction, and arranged in the first...
US-9,960,089 Apparatus and method for endpoint detection
An apparatus to control processing conditions for a substrate. The apparatus may include a current measurement component to perform a plurality of extraction...
US-9,960,088 End point detection in grinding
A method for performing grinding includes selecting a target wheel loading for wafer grinding processes, and performing a grinding process on a wafer. With the...
US-9,960,087 Fabrication of thin-film encapsulation layer for light emitting device
An ink jet process is used to deposit a material layer to a desired thickness. Layout data is converted to per-cell grayscale values, each representing ink...
US-9,960,086 Methods, apparatus and system for self-aligned retrograde well doping for finFET devices
At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) having doping region self-aligned with a fin reveal...
US-9,960,085 Multiple patterning techniques for metal gate
The present disclosure relates to an integrated circuit with a work function metal layer disposed directly on a high-k dielectric layer, and an associated...
US-9,960,084 Method for forming semiconductor device
The present invention provides a method for forming a semiconductor device, comprising the following steps: firstly, a substrate is provided, having a NMOS...
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